Texas Instruments CDC586 3.3-V Phase-Lock-Loop Clock Driver with 3-State Outputs
Summary
The CDC586 is a high-performance, low-skew clock driver utilizing an integrated Phase-Lock Loop (PLL) for precise clock signal distribution. Operating at 3.3V, this device minimizes jitter while reliably distributing one input clock to twelve outputs. It is engineered for high-speed microprocessors and synchronous DRAM applications ranging from 25 MHz up to 100 MHz. The manual provides comprehensive guidance on configuring the PLL via select inputs (SELs) to achieve half or double the input frequency, ensuring optimal synchronization through dedicated feedback channels (FBIN).
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查询CDC586供应商 CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998
Low Output Skew for Clock-Distribution Application for Synchronous DRAM, and Clock-Generation Applications High-Speed Microprocessor Operates at 3.3-V VCC TTL-Compatible Inputs and Outputs Distributes One Clock Input to Twelve Outputs Drive Parallel 50-Ω Terminated Outputs Transmission Lines Two Select Inputs Configure Up to Nine State-of-the-Art EPIC-ΙΙB Bi CMOS Design Outputs to Operate at One-Half or Double Significantly Reduces Power Dissipation the Input Frequency
Distributed VCC and Ground Pins Reduce No External RC Network Required Switching Noise
External Feedback Pin (FBIN) Is Used to Packaged in 52-Pin Thin Quad Flat Package Synchronize the Outputs to the Clock Input
PAH PACKAGE
2Y (TOP VIEW) L1 L0
2Y IN
GND VCC
LK IN
VCC GND GND VCC 1Y2 4Y2
VCC GND
GND VCC 1Y3 4Y1 VCC GND GND GND GND VCC 2Y1 3Y3 VCC GND
NC – No internal connection
description The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC586 operates at 3.3-V VCC and is designed to drive a properly terminated 50- transmission line.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments CDC586 3.3-V Phase-Lock-Loop Clock Driver with 3-State Outputs
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 12 |
| File Size | 149.84 KB |
| Published | July 10, 2026 |
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Frequently Asked Questions
What operating voltages does the CDC586 support?
The device operates at 3.3-V V.
How is synchronization achieved with the PLL?
The feedback input (FBIN) must receive one of the twelve output clocks to maintain synchronization between CLKIN and the outputs.
Does this clock driver require external RC networks?
No, unlike many products containing PLLs, the CDC586 does not require external RC networks; the loop filter is included on chip.
What defines the typical operating temperature range?
The CDC586 is characterized for operation from 0°C to 70°C.