Texas Instruments CDC516 3.3-V Phase-Lock Loop Clock Driver Data Sheet User's Guide
Summary
This advanced clock driver provides robust, low-skew clock distribution for synchronous DRAM applications operating at 3.3V. Utilizing an integrated Phase-Lock Loop (PLL), the CDC516 ensures precise phase alignment by distributing one central clock signal to four independent banks of outputs. The manual details how external engineers can leverage this device's high-speed functionality, separate output enable controls, and low-jitter performance to simplify complex PCB designs, making it essential for reliability in memory subsystem designs.
Page 1 Text Content
查询CDC516供应商 CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
Phase-Lock Loop Clock Distribution for DGG PACKAGE (TOP VIEW)
Synchronous DRAM Applications Distributes One Clock Input to Four Banks
VCC VCC
of Four Outputs
Separate Output Enable for Each Output
GND GND
External Feedback Pin (FBIN) Is Used to
GND GND
Synchronize the Outputs to the Clock Input
No External RC Network Required 1Y3 4Y3
Operates at 3.3-V VCC VCC VCC 1G 4G
Packaged in Plastic 48-Pin Thin Shrink
GND GND
Small-Outline Package
AVCC AVCC description CLK FBIN AGND AGND
The CDC516 is a high-performance, low-skew, AGND FBOUT low-jitter, phase-lock loop clock driver. It uses a
GND GND
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the feedback output
VCC VCC
(FBOUT) to the clock (CLK) input signal. It is
specifically designed for use with synchronous
DRAMs. The CDC516 operates at 3.3-V VCC and
GND GND
is designed to drive up to five clock loads per
GND GND
output.
2Y2 3Y2 Four banks of four outputs provide 16 low-skew, 2Y3 3Y3 low-jitter copies of the input clock. Output signal VCC VCC
duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground. The CDC516 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments CDC516 3.3-V Phase-Lock Loop Clock Driver Data Sheet User's Guide
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 11 |
| File Size | 144.11 KB |
| Published | July 16, 2026 |
Enter the captcha to get the download link:
Frequently Asked Questions
What must be done after powering up or changing PLL signals?
A stabilization time is required to achieve phase lock of the feedback signal to the reference signal.
Does the CDC516 need external components for its PLL function?
No external RC network is needed because the loop filter for the PLL is included on-chip.