Texas Instruments CDC582 3.3-V Phase-Locked Loop Clock Driver with Differential LVPECL Clock Inputs

Summary

The CDC582 is a high-performance, low-skew phase-locked loop (PLL) clock driver designed for precise timing distribution in demanding electronics. Accepting differential LVPECL inputs, this device synchronizes and distributes stable, low-jitter clock signals across up to twelve TTL-compatible outputs at 3.3V. It is ideally suited for signal applications like Synchronous DRAMs that require stable frequency matching, offering configurable output frequencies (half or double) while minimizing external components. The manual details its PLL operation, synchronization mechanics, and advanced output control features.

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查询CDC582供应商 CDC582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS446B – JULY 1994 – REVISED FEBRUARY 1996

Low Output Skew for Clock-Distribution State-of-the-Art EPIC-ΙΙB Bi CMOS Design and Clock-Generation Applications Significantly Reduces Power Dissipation Operates at 3.3-V VCC External Feedback Input (FBIN) Is Used to

Synchronize the Outputs With the Clock

Distributes Differential LVPECL Clock

Inputs

Inputs to 12 TTL-Compatible Outputs

Application for Synchronous DRAMs

Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double Distributed VCC and Ground Pins Reduce the Input Frequency Switching Noise No External RC Network Required Packaged in 52-Pin Quad Flatpack

PAH PACKAGE (TOP VIEW)

GND VCC

2Y IN

1Y1 4Y3 VCC GND GND VCC

LK IN

3Y LK IN

VCC GND GND VCC 1Y3 4Y1

VCC GND

GND GND GND VCC 2Y1 3Y3 VCC GND

description The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC582 operates at 3.3-V VCC. The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN) signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized to the same frequency as the clock (CLKIN and CLKIN) inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page Summary Contents For Texas Instruments CDC582 3.3-V Phase-Locked Loop Clock Driver with Differential LVPECL Clock Inputs

Page 1 查询CDC582供应商 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 Low Output Skew for Clock-Distribution State-of-the-Art EPIC-ΙΙ...

Page 2 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 description (continued) The Y outputs can be configured to switch in phase ...

Page 3 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 output configuration B Output configuration B is valid when any output conf...

Page 4 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 functional block diagram ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ Phase-Lock Loop ÁÁÁ CLKIN CLKIN One...

Page 5 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. Clock input. CLKIN and...

Page 6 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply volta...

Page 7 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 timing requirements over recommended ranges of supply voltage and operating...

Page 8 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 PARAMETER MEASUREMENT INFORMATION CLKIN CLKIN tphase error 1 Outputs Operat...

Page 9 CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS446B – JULY 1994 – REVISED FEBRUARY 1996 PARAMETER MEASUREMENT INFORMATION CLKIN CLKIN tphase error 10 Outputs Opera...

Page 10 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain...

Manual Details

Brand	Texas Instruments
Pages	10
File Size	128.12 KB
Published	June 17, 2026

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Frequently Asked Questions

What voltage does the CDC582 operate on?

The device operates at a regulated 3.3-V voltage.

How is clock synchronization achieved?

Feedback (FBIN) synchronizes the output clocks to the input differential LVPECL signals by requiring one output to be wired back to FBIN for the PLL.

Does the CDC582 require any external components?

No, the loop filter for the PLL is included on-chip, and no external RC networks are required.

What must I do before using the device after power up or setting changes?

The CDC582 requires a specific stabilization time following power up and modifications to the CLKIN/CLKIN signals (SEL1/SEL0 change) to achieve phase lock.