Texas Instruments CDC2509B 3.3-V Phase-Lock Loop Clock Driver Data Sheet

查询CDC2509B供应商 CDC2509B

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS613 – SEPTEMBER 1998

Designed to Meet PC SDRAM Registered PW PACKAGE (TOP VIEW)

DIMM Specification Spread Spectrum Clock Compatible

AGND CLK

Operating Frequency 25 MHz to 125 MHz

VCC AVCC

t Phase Error Minus Jitter at 66MHz to 1Y0 VCC 100 MHz is ±150 ps 1Y1 2Y0

Jitter (pk – pk) at 66 MHz to 100 MHz is 1Y2 2Y1 ±80 ps GND GND GND GND

Jitter (cyc – cyc) at 66 MHz to 100 MHz is

|100 ps|

Available in Plastic 24-Pin TSSOP

VCC VCC

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

FBOUT FBIN

Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3-V

description The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2509B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDC2509B is characterized for operation from 0°C to 70°C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

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PRODUCTION DATA information is current as of publication date. Copyright  1998, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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