Texas Instruments CDC536 3.3-V Phase-Lock Loop Clock Driver with 3-State Outputs
Summary
The CDC536 is a high-performance, low-skew clock driver utilizing an integrated Phase-Lock Loop (PLL). It is designed for advanced system designers who need precise synchronization and distribution of single clock signals to multiple outputs in high-speed digital environments. This manual provides comprehensive details on setting up frequency and phase alignment using its PLL architecture, supporting applications ranging from Synchronous DRAM to high-speed microprocessors operating at 3.3V. Key features include automatic output configuration (half or double input frequency) and no requirement for external RC networks, ensuring reliable clock distribution in complex PCBs.
Page 1 Text Content
查询CDC536供应商 CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS SCAS378F – APRIL 1994 – REVISED OCTOBER 1998 Low-Output Skew for Clock-Distribution DB OR DL PACKAGE (TOP VIEW)
and Clock-Generation Applications Operates at 3.3-V VCC
AVCC AVCC
Distributes One Clock Input to Six Outputs
AGND AGND
One Select Input Configures Three Outputs
CLKIN FBIN
to Operate at One-Half or Double the Input
SEL TEST
Frequency
OE CLR
No External RC Network Required GND VCC
External Feedback Pin (FBIN) Is Used to 1Y1 2Y1 Synchronize the Outputs to the Clock Input VCC GND
GND VCC
Application for Synchronous DRAM,
High-Speed Microprocessor
VCC GND
Negative-Edge-Triggered Clear for
GND VCC
Half-Frequency Outputs
TTL-Compatible Inputs and Outputs
VCC GND
Outputs Drive 50-Ω Parallel-Terminated Transmission Lines State-of-the-Art EPIC-ΙΙB Bi CMOS Design Significantly Reduces Power Dissipation Distributed VCC and Ground Pins Reduce Switching Noise Packaged in Plastic 28-Pin Shrink Small Outline Package
description The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50- transmission line. The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation. Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments CDC536 3.3-V Phase-Lock Loop Clock Driver with 3-State Outputs
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 12 |
| File Size | 153.23 KB |
| Published | June 02, 2026 |
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Frequently Asked Questions
How is PLL synchronization achieved with this device?
The CDC536 requires that one of the six Y outputs be externally wired to the FBIN pin to complete the PLL feedback loop.
Does the clock driver require external resistor/capacitor components?
No, external RC networks are not required as the loop filter for the PLL is included directly on-chip.
What operational delay should I account for when powering up the CDC536?
The device needs a stabilization time following power up or signal changes to achieve phase lock of the feedback signal.