Texas Instruments CDC2516 3.3-V Phase-Lock Loop Clock Driver Data Sheet User Manual

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

Phase-Lock Loop Clock Distribution for DGG PACKAGE (TOP VIEW)

Synchronous DRAM Applications Distributes One Clock Input to Four Banks

VCC VCC

of Four Outputs

Separate Output Enable for Each Output

GND GND

External Feedback Pin (FBIN) Is Used to

GND GND

Synchronize the Outputs to the Clock Input

On-Chip Series-Damping Resistors 1Y3 4Y3

No External RC Network Required VCC VCC 1G 4G

Operates at 3.3-V VCC

GND GND

Packaged in Plastic 48-Pin Thin Shrink

AVCC AVCC

Small-Outline Package

CLK FBIN AGND AGND

description

AGND FBOUT The CDC2516 is a high-performance, low-skew, GND GND low-jitter, phase-lock loop (PLL) clock driver. It 2G 3G uses a PLL to precisely align, in both frequency VCC VCC and phase, the feedback output (FBOUT) to the 2Y0 3Y0

clock (CLK) input signal. It is specifically designed 2Y1 3Y1 for use with synchronous DRAMs. The CDC2516 GND GND operates at 3.3-V VCC and provides integrated GND GND series-damping resistors that make it ideal for 2Y2 3Y2 driving point-to-point loads. 2Y3 3Y3

VCC VCC

Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground. The CDC2516 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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