Texas Instruments CDC9842 PC Motherboard Clock Synthesizer Driver with 3-State Outputs

查询CDC9842供应商 CDC9842

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS SCAS546B – NOVEMBER 1995 – REVISED MAY 1996 Provides System Clock Solution for DW PACKAGE (TOP VIEW)

Pentium/82430X/82430VX and Pentium Pro 82440FX Chipsets

VCC REF0

Four Host-Clock Outputs With

X1 REF1

Programmable Frequency (50 MHz, 60 MHz

X2 VCC

and 66 MHz)

GND REF2

Six PCI Clock Outputs at Half-CPU

OE SBCLK

Frequency

HCLK0 GND

One 48-MHz Universal Serial Bus (USB)

HCLK1 PCLK0

Clock Output

VCC PCLK1

Three 14.318-MHz Reference Clock Outputs HCLK2 VCC

All Output Clock Frequencies Derived From HCLK3 PCLK2 a Single 14.31818-MHz Crystal Input GND PCLK3 SEL1 GND

LVTTL-Compatible Inputs and Outputs

SEL0 PCLK4

Internal Loop Filters for Phase-Locked

VCC PCLK5

Loops Eliminate the Need for External Components Operates at 3.3 VCC Packaged in Plastic Small-Outline Package

description The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support Pentium/82430X/82430VX and Pentium Pro 82440FX chipsets. Four host-clock outputs (HCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided. All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the X1 input instead of a crystal input. Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock frequency is derived directly from the host-clock frequency. The PLL circuit can be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input. The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE. Because the CDC9842 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the OE or SELn inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pentium is a trademark of Intel Corporation.

Copyright  1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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