Texas Instruments SN74LVC16646 16-Bit Bus Transceiver and Register with 3-State Outputs

查询SN74LVC16646供应商 SN74LVC16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS SCAS318B – NOVEMBER 1993 – REVISED JULY 1995 Member of the Texas Instruments DGG OR DL PACKAGE (TOP VIEW)

Widebus Family EPIC  (Enhanced-Performance Implanted

1DIR 1OE

CMOS) Submicron Process

1CLKAB 1CLKBA

Typical VOLP (Output Ground Bounce)

1SAB 1SBA

< 0.8 V at VCC = 3.3 V, TA = 25°C

GND GND

Typical VOHV (Output VOH Undershoot)

> 2 V at VCC = 3.3 V, TA = 25°C

1A2 1B2 Latch-Up Performance Exceeds 250 m A VCC VCC

Per JEDEC Standard JESD-17 1A3 1B3

Bus Hold on Data Inputs Eliminates the 1A4 1B4 Need for External Pullup/Pulldown 1A5 1B5 Resistors GND GND 1A6 1B6

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

2A1 2B1 description 2A2 2B2 2A3 2B3

This 16-bit bus transceiver and register is

GND GND

designed for low-voltage (3.3-V) VCC operation.

The SN74LVC16646 can be used as two 8-bit

transceivers or one 16-bit transceiver. The device

consists of bus transceiver circuits, D-type VCC VCC flip-flops, and control circuitry arranged for 2A7 2B7 multiplexed transmission of data directly from the 2A8 2B8 input bus or from the internal registers. GND GND 2SAB 2SBA

Data on the A or B bus is clocked into the registers

2CLKAB 2CLKBA

on the low-to-high transition of the appropriate

2DIR 2OE

clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC16646. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The SN74LVC16646 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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