Motorola MC10E155 MC100E155 Data Manual

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

6-BIT 2:1

850ps Max. LEN to Output

MUX-LATCH

825ps Max. D to Output Single-Ended Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

VCCONCD3a D3b D4a D4b D5a FN SUFFIX

PLASTIC PACKAGE CASE 776-02

LEN1 Q4

LOGIC DIAGRAM

LEN2 VCC D0a Q0

VEE Q3 D0b SEL

MR Q2 D1a

MUX Q1

SEL VCCO D1b SEL

D2b SEL

D0b D1a D1b D2a D2b VCCO Q0

MUX Q3

* All VCC and VCCO pins are tied together on the die.

D3b SEL

PIN NAMES D4a

MUX Q4

Pin Function

D0a D04 Input Data a

D0b D4b Input Data b D5a

SEL Data Select Input

LEN1, LEN2 Latch Enables

D5b SEL

MR Master Reset Q0 Q4 Outputs SEL

TRUTH TABLE LEN1

SEL Data

2–1 REV 3 Motorola, Inc. 1996