Fairchild 74VHC00 Quad 2-Input NAND Gate Data Manual

74V 00 — ad 2-In t N ate

February 2008

74VHC00 Quad 2-Input NAND Gate Features General Description High Speed: t PD = 3.7ns (typ.) at TA = 25°C The VHC00 is an advanced high-speed CMOS 2-Input

High noise immunity: VNIH = VNIL = 28% VCC (min.) NAND Gate fabricated with silicon gate CMOS technol- ogy. It achieves the high-speed operation similar to

Power down protection is provided on all inputs

equivalent Bipolar Schottky TTL while maintaining the

Low noise: VOLP = 0.8V (max)

CMOS low power dissipation. The internal circuit is com-

Low power dissipation: ICC = 2µA (max.) at TA = 25°C

posed of 3 stages, including buffer output, which provide

Pin and function compatible with 74HC00 high noise immunity and stable output. An input protec-

tion circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

Ordering Information

Package

Order Number Number Package Description 74VHC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

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74VHC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

©1 992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74V HC00 Rev. 1.3.0