Fairchild 74VHC132 Quad 2-Input NAND Schmitt Trigger Data Manual

74V 132 — ad 2-In t N ch itt Trig er

December 2007

74VHC132 Quad 2-Input NAND Schmitt Trigger Features General Description High Speed: t PD = 3.9ns (Typ.) at VCC = 5V The VHC132 is an advanced high speed CMOS 2-input

Power down protection is provided on all inputs NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation

Low power dissipation: ICC = 2µA (Max.) at TA = 25°C

similar to Bipolar Schottky TTL while maintaining the

Low noise: VOLP = 0.8V (Max.)

CMOS low power dissipation. Pin configuration and

Pin and function compatible with 74HC132

function are the same as the VHC00 but the inputs have hysteresis between the positive-going and negative- going input thresholds, which are capable of transform- ing slowly changing input signals into sharply defined, jitter-free output signals. Thus greater noise margin then conventional gates is provided. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

Ordering Information

Package

Order Number Number Package Description 74VHC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

©1 995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74V HC132 Rev. 1.5.0