Texas Instruments XIO1100 Data Manual
Summary
The comprehensive technical manual for the XIO1100 component provides essential specifications for system designers and electrical engineers. It details the functional capabilities, power management configurations (P0, P1), accurate clock handling, and reliable reset protocols required for product integration. Use this resource to ensure optimal performance when designing sophisticated electronic circuits with Texas Instruments components.
Page 1 Text Content
XIO1100
Data Manual
Literature Number: SLLS690B
June 2006
Page Summary Contents For Texas Instruments XIO1100 Data Manual
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XIO1100 Data Manual Literature Number: SLLS690B June 2006
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and servic...
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Contents Contents Section Page XIO1100 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Descripti...
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List of Figures Figure Page Figure 2−1. XIO1100 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4−1. TI−PIPE Input Ti...
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List of Tables Table Page Table 2−1. Clock Selection 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2−2. R...
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Features XIO1100 Features X1 PCI Express Serial Link TI-PIPE MAC Interface − PCI Express 1.1 Compliant − Source-Synchronous TX and RX Ports − Selectable Reference Clock (100 MHz, − 125 MHz TX/RX Cloc...
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Description 2.2 Functional Description The XIO1100 meets all of the requirements for a PCI−Express PHY as defined by Section 4, Physical Layer Specifications, of the PCI−SIG document PCI Express Base ...
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Description 2.3.1 P0 P0 is the normal operation state for the XIO1100. The POWERDOWN[1:0] input signals define which of the three power states that an XIO110 is in at any given time. In states P0, P0s...
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Description 2.6 Receiver Detection While in the P1 power state, XIO1100 can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. Th...
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Description 2.8.1 8B/10B Decode Error When XIO1100 detects an 8B/10B decode error, it asserts an EDB (0x FE) symbol in the data on the RX_DATA[15:0] where the bad byte occurred (only the erroneous byt...
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Description 2.13 Terminal Assignments The XIO1100 is packaged in a 100-pin GGB BGA package. See Section 6 for GGB-package terminal diagram. Table 2−3 lists the terminal assignments in terminal-number ...
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Description Table 2−4. 100-pin GGB Signal Name Sorted Alphabetically SIGNAL NAME GGB SIGNAL NAME GGB SIGNAL NAME GGB SIGNAL NAME GGB NUMBER NUMBER NUMBER NUMBER CLK_SEL L6 RX_DATA8 A3 TX_DATA6 M3 VDD_...
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Description 2.14 Terminal Descriptions Table 2−5 describes the XIO1100 terminals. The terminals are grouped by functionality. Table 2−5. XIO1100 Terminals TERMINAL I/O DESCRIPTION NAME NO. PIPE INTERF...
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Description Table 2−5. XIO1100 Terminals (Continued) TERMINAL DESCRIPTIONI/O TX_ELECIDLE N9 Forces TXN/TXP outputs to electrical idle. When de−asserting low while in P0 state (POWERDOWN[1:0] = 00), in...
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Description Table 2−5. XIO1100 Terminals (Continued) TERMINAL DESCRIPTIONI/O RX_STATUS[2:0] G3, G1, E3 Encodes receiver status and error codes for the received data stream and receive detection, as fo...
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Description Table 2−5. XIO1100 Terminals (Continued) TERMINAL DESCRIPTIONI/O CLK_SEL L6 Clock Select This input, when asserted low during /RESET transitioning from low to high, selects the 100 MHz dif...
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Electrical Characteristics Electrical Characteristics 3.1 Absolute Maximum Ratings† Supply voltage range: 3.3 V Supply −0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Characteristics 3.3 PCI Express Differential Transmitter Output Ranges PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS UI TXP, TXN 399.88 400.12 ps Each UI is 400 ps ±300 ppm. UI does not acc...
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Electrical Characteristics PARAMETER COMMENTSUNITMAXNOMMINTERMINALS VTX–IDLE–DIFFp TXP, TXN m V VTX–IDLE–DIFFp = |VTXP–Idle − VTXN–Idle| ≤ 20 m V Electrical idle differen- See Note 5. tial peak output...
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Electrical Characteristics PARAMETER COMMENTSUNITMAXNOMMINTERMINALS ZTX–DC TXP, TXN Required TXP as well as TXN dc impedance during all states Transmitter dc imped- ance CTX TXP, TXN n F All transmitt...
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Electrical Characteristics PARAMETER COMMENTSUNITMAXNOMMINTERMINALS TRX–EYE–MEDIAN–to–MAX–JITTER RXP, RXN 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX–DIFFp–p = 0 ...
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Electrical Characteristics PARAMETER COMMENTSUNITMAXNOMMINTERMINALS VRX–IDLE–DET–DIFFp–p RXP, RXN m V VRX–IDLE–DET–DIFFp–p = 2*|VRXP − VRXN| measured at the receiver package terminals Electrical idle ...
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Electrical Characteristics 3.5 Express Differential Reference Clock Input Ranges PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS f IN–DIFF REFCLK+ MHz The input frequency is 100 MHz + 300 ppm and − 2800...
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Electrical Characteristics 3.6 Electrical Characteristics Over Recommended Operating Conditions (VDD_IO) PARAMETER OPERATION MIN TYP MAX UNIT CONDITIONS VIH High-level input voltage (Note 16) VDD_IO 0...
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Timing Diagrams Timing Diagrams TI−PIPE Input Timing TX_CLK Tx Data[7:0] (DDR mode) Tx Data K[0] (DDR mode) tfsu trsu tfh tfh Tx Data[15:0] (SDR mode) Tx Data K[1:0] (SDR mode) Tx Detect Rx/Loopback T...
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Timing Diagrams TI−PIPE Data Output Timing RX_CLK Rx Data[7:0] (DDR mode) Rx Data K[0] (DDR mode) trco tfh tfh Rx Data[15:0] (SDR mode) Rx Data K[1:0] (SDR mode) Rx Valid Phy Status Rx Elec Idle Rx St...
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Timing Diagrams TI−PIPE Output Functional Timing RX_CLK Rx Data[7:0] (DDR mode) SYMBOL (N) SYMBOL (N+1) Rx Data K[0] (DDR mode) Rx Data[15:0] (SDR mode) Rx Data[7:0] − SYMBOL (N) Rx Data K[1:0] (SDR m...
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Timing Diagrams TI−PIPE Input Functional Timing TX_CLK Tx Data[7:0] (DDR mode) SYMBOL (N) SYMBOL (N+1) Tx Data K[0] (DDR mode) Tx Data[15:0] (SDR mode) Tx Data[7:0] − SYMBOL (N) Tx Data K[1:0] (SDR mo...
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Application Information Application Information 5.1 Component Connection Details regarding connection of components to the various terminals of the XIO1100 are discussed primarily in entries for each ...
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Application Information 5.2 XIO1100 Component Placement The filter network on VDD_33_COMB, VDD_33_COMB_IO, and VDD_15_COMB needs to be placed as close as possible to each pin (specifically H11, L13, a...
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Application Information 5. When designing filters associated with power distribution, the power supply is a low-impedance source, and the device power terminals are a low-impedance load. The best filt...
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Application Information 5.4 PCIe Layout Guidelines The XIO1100 TXP and TXN terminals comprise a low-voltage, 100-Ω differentially driven signal pair. The RXP and RXN terminals for the XIO1100 receive ...
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Application Information The XIO1100 is optimized for this type of system clock design. The REFCLK+ and REFCLK− terminals provide differential reference clock inputs to the XIO1100. The circuit board r...
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Mechanical Data Mechanical Data SLLS690B 29June 2006
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PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing Qty XIO1100GGB ACTIVE BGA ...
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 36 |
| File Size | 456.00 KB |
| Published | July 16, 2026 |
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