Texas Instruments CDC950 Data Sheet / Manual

查询CDC950DGGG4供应商

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

Generates Clocks for Next Generation DGG PACKAGE (TOP VIEW)

Microprocessors Uses a 14.318-MHz Crystal Input to

CLK33 SEL100/133

Generate Multiple Output Frequencies

VDD3.3V GND

Includes Spread Spectrum Clocking (SSC), 3V48/Sel A AVDD3.3V 0.6% Downspread for Reduced EMI With 3V48/Sel B AGND Theoretical EMI of 7 d B

GND PWRDWN

Power Management Control Terminals VDD3.3V VDD3.3V HCLK(0) HCLK(4)

Low Output Skew and Jitter for Clock

Distribution HCLK(0) HCLK(4) GND GND

Operates From a Single 3.3-V Supply

HCLK(1) HCLK(5)

Generates the Following Clocks:

HCLK(1) HCLK(5)

− 8 Host (Diff Pairs, 100/133 MHz)

VDD3.3V VDD3.3V

− 1 CLK33 (3.3 V, 33.3 MHz)

HCLK(2) HCLK(6)

− 1 REFCLK (3.3 V, 14.318 MHz)

HCLK(2) HCLK(6)

− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)

GND GND

Packaged in a 48-Pin TSSOP Package

HCLK(3) HCLK(7) HCLK(3) HCLK(7)

description

VDD3.3V VDD3.3V The CDC950 is a differential clock synthesizer/ REFCLK Mult Sel0 driver that generates HCLK/HCLK, CLK33, 3V48, SPREAD Mult Sel1

and REFCLK system clock signals to support a GND GND computer system with next generation processors XIN AGND and double data rate (DDR) memory subsystems. XOUT I_REF VDD3.3V AVDD3.3V

All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133, 3V48/Sel A, and 3V48/Sel B. The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers down completely with the HOST clock at 2 × IREF, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are in a low-level output state and 3V48B is in a high-level output state. The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz. Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as following changes to the SEL inputs. With the use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time starts. The CDC950 is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2001 − 2003, Texas Instruments Incorporated
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