ST LNBH26S Dual LNBS Supply and Control IC with Step-up and I²C Interface Data Sheet User Manual

Summary

This advanced interface IC provides a comprehensive solution for dual-tuner satellite receiving systems. It manages both the power supply and I²C communication protocols, integrating features like 22 kHz tone generation and built-in diagnostic protections (e.g., overcurrent/overtemperature protection). The manual serves as an essential technical guide, detailing signal encoding methods (DiSEqC data), electrical requirements, and the specific implementation of the I²C bus interface. It is designed for electrical engineers developing Sat-TV receivers, Set-Top Boxes (STBs), or satellite smart cards needing high efficiency and low component count in a single IC solution.

Table 1. Device summary
1 Block diagram
- Figure 1. Block diagram
2 Application information (valid for each section A/B)
- 2.1 DISEQC data encoding (DSQIN pin)
- 2.2 Data encoding by external 22 kHz tone TTL signal
  - Figure 2. Tone enable and disable timing (using external waveform)
- 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin
  - Figure 3. Tone enable and disable timing (using envelope signal)
- 2.4 Output current limit selection
- 2.5 Output voltage selection
- 2.6 Diagnostic and protection functions
- 2.7 Surge protection and TVS diodes
  - Figure 4. Surge protection circuit
- 2.8 Power-on I·C interface reset and undervoltage lockout
- 2.9 PNG: input voltage minimum detection
- 2.10 OLF: overcurrent and short-circuit protection and diagnostic
- 2.11 OTF: thermal protection and diagnostic
3 Pin configuration
- Figure 5. Pin connections (top view)
- Table 2. Pin description
4 Maximum ratings
- Table 3. Absolute maximum ratings
- Table 4. Thermal data
5 Typical application circuits
- Figure 6. LNBH26S DiSEqC 1.X typical application circuit
- Table 5. LNBH26S DiSEqC 1.x bill of material
6 I·C bus interface
- 6.1 Data validity
- 6.2 START and STOP condition
- 6.3 Byte format
- 6.4 Acknowledge
- 6.5 Transmission without acknowledge
  - Figure 7. Data validity on the I·C bus
  - Figure 8. Timing diagram of I·C bus
  - Figure 9. Acknowledge on the I·C bus
7 I·C interface protocol
- 7.1 Write mode transmission
  - Figure 10. Example of writing procedure starting with first data address 0x2
- 7.2 Read mode transmission
  - Figure 11. Example of reading procedure starting with first status address 0X0
- 7.3 Data registers
  - Table 6. DATA 1 (read/write register. Register address = 0X2)
  - Table 7. DATA 2 (read/write register. Register address = 0X3)
  - Table 8. DATA 3 (read/write register. Register address = 0X4)
  - Table 9. DATA 4 (read/write register. Register address = 0X5)
- 7.4 Status registers
  - Table 10. STATUS 1 (read register. Register address = 0X0)
  - Table 11. STATUS 2 (read register. Register address = 0X1)
8 Electrical characteristics
- Table 12. Electrical characteristics of section A/B
- 8.1 Output voltage selection
  - Table 13. Output voltage selection table (Data1 register, write mode)
  - Table 14. I·C electrical characteristics
  - Table 15. Address pin characteristics
9 Package mechanical data
- Table 16. QFN24L (4x4 mm) mechanical data
- Figure 12. QFN24L (4x4 mm) package dimensions
- Figure 13. QFN24L (4x4) footprint recommended data (mm)
10 Revision history
- Table 17. Document revision history

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Page 1 Text Content

LNBH26S

Dual LNBS supply and control IC with step-up and I²C interface

Datasheet − preliminary data

Features Complete interface between LNB and I²C bus Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A) Selectable output current limit by external resistor Compliant with main satellite receiver output voltage specification (8 programmable levels)

QFN24 (4x4 mm)

Accurate built-in 22 k Hz tone generator suits widely accepted standards 22 k Hz tone waveform integrity guaranteed also at no load condition Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS Description allowing low power losses

Intended for analog and digital DUAL satellite

Overload and overtemperature internal

receivers/Sat-TV, Sat-PC cards, the LNBH26S is

protection with I²C diagnostic bits

a monolithic voltage regulator and interface IC,

LNB short-circuit dynamic protection

assembled in QFN24 (4x4) specifically designed +/- 4 k V ESD tolerant on output power pins to provide the 13 / 18 V power supply and the 22 k Hz tone signalling to the LNB down-converter in the antenna dishes or to the multi-switch box. In

Applications

this application field, it offers a complete solution for dual tuner satellite receivers with an extremely

STB satellite receivers

low component count and low power dissipation

TV satellite receivers

together with simple design and I²C standard

PC card satellite receivers interfacing.

Table 1. Device summary

Order code Package Packaging

LNBH26SPQR QFN24 (4x4) Tape and reel

March 2012 Doc ID 022995 Rev 1 1/29 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com change without notice.

Page Summary Contents For ST LNBH26S Dual LNBS Supply and Control IC with Step-up and I²C Interface Data Sheet User Manual

Page 1 LNBH26S Dual LNBS supply and control IC with step-up and I²C interface Datasheet − preliminary data Features Complete interface between LNB and I²C bus Built-in DC-DC converter for single 12 V supply ...

Page 2 Contents LNBH26S Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application information (valid for each section A/B) . . . . . . ....

Page 3 LNBH26S Contents 7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . ...

Page 4 Block diagram LNBH26S 1 Block diagram Figure 1. Block diagram Is en se DSQIN-A ADDR SDASCL DSQIN-B LX-A LX-B at ct rl PW TR I²C Digital core DAC Drop control PGND PGND Tone ctrl Diagnostics VUP-A Prot...

Page 5 LNBH26S Application information (valid for each section A/B) 2 Application information (valid for each section A/B) This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16...

Page 6 Application information (valid for each section A/B) LNBH26S Figure 2. Tone enable and disable timing (using external waveform) DSQIN Tone Output AM10426v1 2.3 Data encoding by external Di SEq C envel...

Page 7 LNBH26S Application information (valid for each section A/B) 2.5 Output voltage selection Each linear regulator channel output voltage level can be easily programmed in order to accomplish application...

Page 8 Application information (valid for each section A/B) LNBH26S 2.8 Power-on I²C interface reset and undervoltage lockout The I²C interface built into the LNBH26S is automatically reset at power-on. As l...

Page 9 LNBH26S Application information (valid for each section A/B) 2.11 OTF: thermal protection and diagnostic The LNBH26S is also protected against overheating: when the junction temperature exceeds 150 °C...

Page 10 Pin configuration LNBH26S 3 Pin configuration Figure 5. Pin connections (top view) GNDDSQIN-B DSQIN-A VUP-A VOUT-A GND GND GND GND VCC LX-A BYP PGND GND ADDR GND SCL SDA ISEL VUP-B VOUT-BNC AM11885v1 ...

Page 11 LNBH26S Pin configuration Table 2. Pin description (continued) Pin n° Symbol Name Pin function GND Analog ground Analog circuits ground. To be connected directly to the Epad. Not internally N.C. Not i...

Page 12 Maximum ratings LNBH26S 4 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC power supply input voltage pins -0.3 to 20 VUP DC input voltage -0.3 to 40 IOUT Output cu...

Page 13 LNBH26S Typical application circuits 5 Typical application circuits Figure 6. LNBH26S Di SEq C 1.X typical application circuit LNBOUT-A VUP-A VOUT-A C2-A C3-A LNBH26SD1-A C5-A D3-A R1 (RSEL) Di SEq C ...

Page 14 I²C bus interface LNBH26S 6 I²C bus interface Data transmission from the main microprocessor to the LNBH26S, and vice versa, takes place through the 2-wire I²C bus interface, consisting of the 2-line ...

Page 15 LNBH26S I²C bus interface Figure 7. Data validity on the I²C bus Figure 8. Timing diagram of I²C bus Figure 9. Acknowledge on the I²C bus Doc ID 022995 Rev 1 15/29

Page 16 I²C interface protocol LNBH26S 7 I²C interface protocol /A /A 7.1 Write mode transmission /A LR /A The LNBH26S interface protocol is made up of: a START condition (S) TH ER a chip address byte with th...

Page 17 LNBH26S I²C interface protocol 7.2 Read mode transmission In read mode the bytes sequence must be as follows: /A /A a START condition (S) a chip address byte with the LSb bit R/W=0 LR /A the register ...

Page 18 I²C interface protocol LNBH26S 7.3 Data registers The DATA 1..4 registers can be addressed both in write and read mode. In read mode they return the last writing byte status received in the previous w...

Page 19 LNBH26S I²C interface protocol Table 8. DATA 3 (read/write register. Register address = 0X4) Bit Name CH Value Description Bit 0 N/A Reserved. Keep to “0” (LSb) Bit 1 N/A Reserved. Keep to “0” Bit 2 P...

Page 20 I²C interface protocol LNBH26S 7.4 Status registers The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables. Table 10. STATU...

Page 21 LNBH26S Electrical characteristics 8 Electrical characteristics Refer to Section 5, TJ from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1, RSEL = 11 kΩ, DSQIN = LOW, VIN = 12 V, IO...

Page 22 Electrical characteristics LNBH26S Table 12. Electrical characteristics of section A/B (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VLP threshold rising 7.2 Low power diagnostic (L...

Page 23 LNBH26S Electrical characteristics Table 13. Output voltage selection table (Data1 register, write mode) (1) VOUT -A/B VSEL4- VSEL3- VSEL2- VSEL1- VOUT VOUT pin Function A/B A/B A/B A/B min. max. volt...

Page 24 Package mechanical data LNBH26S 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of env...

Page 25 LNBH26S Package mechanical data Figure 12. QFN24L (4x4 mm) package dimensions Doc ID 022995 Rev 1 25/29

Page 26 Package mechanical data LNBH26S Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Min. Typ. Max. Min. Typ. Max. Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 0.157 26/29 Doc ID 022995 Rev 1

Page 27 LNBH26S Package mechanical data Figure 13. QFN24L (4x4) footprint recommended data (mm) Doc ID 022995 Rev 1 27/29

Page 28 Revision history LNBH26S 10 Revision history Table 17. Document revision history Date Revision Changes 27-Mar-2012 Initial release. 28/29 Doc ID 022995 Rev 1

Page 29 LNBH26S Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corr...

Manual Details

Brand	Dual
Pages	29
File Size	921.83 KB
Published	May 31, 2026

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Frequently Asked Questions

What kind of signal does the LNBH26S support for data transmission?

It includes a complete interface between the LNB and I²C bus, supporting various encoding methods using the DSQIN pin.

Does the unit have built-in power regulation capabilities?

Yes, it features a built-in DC-DC converter for single 12 V supply operation and low-drop post regulator.

What types of applications is this IC suitable for?

It is intended for dual satellite receivers—including Sat-TV, Sat-PC cards, and STB receivers—due to its simple design and I²C standard.

How can the user adjust the electrical output parameters?

The output current limit can be selected using an external resistor, while the output voltage selection is also adjustable.

ST LNBH26S Dual LNBS Supply and Control IC with Step-up and I²C Interface Data Sheet User Manual

Summary

Figure 2. Tone enable and disable timing (using external waveform)

Figure 3. Tone enable and disable timing (using envelope signal)

Figure 4. Surge protection circuit

Figure 7. Data validity on the I·C bus

Figure 8. Timing diagram of I·C bus

Figure 9. Acknowledge on the I·C bus

Figure 10. Example of writing procedure starting with first data address 0x2

Figure 11. Example of reading procedure starting with first status address 0X0

Table 6. DATA 1 (read/write register. Register address = 0X2)

Table 7. DATA 2 (read/write register. Register address = 0X3)

Table 8. DATA 3 (read/write register. Register address = 0X4)

Table 9. DATA 4 (read/write register. Register address = 0X5)

Table 10. STATUS 1 (read register. Register address = 0X0)

Table 11. STATUS 2 (read register. Register address = 0X1)

Table 13. Output voltage selection table (Data1 register, write mode)

Table 14. I·C electrical characteristics

Table 15. Address pin characteristics

Table 1. Device summary

1 Block diagram

Figure 1. Block diagram

2 Application information (valid for each section A/B)

2.1 DISEQC data encoding (DSQIN pin)

2.2 Data encoding by external 22 kHz tone TTL signal

Figure 2. Tone enable and disable timing (using external waveform)

2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin

Figure 3. Tone enable and disable timing (using envelope signal)

2.4 Output current limit selection

2.5 Output voltage selection

2.6 Diagnostic and protection functions

2.7 Surge protection and TVS diodes

Figure 4. Surge protection circuit

2.8 Power-on I·C interface reset and undervoltage lockout

2.9 PNG: input voltage minimum detection

2.10 OLF: overcurrent and short-circuit protection and diagnostic

2.11 OTF: thermal protection and diagnostic

3 Pin configuration

Figure 5. Pin connections (top view)

Table 2. Pin description

4 Maximum ratings

Table 3. Absolute maximum ratings

Table 4. Thermal data

5 Typical application circuits

Figure 6. LNBH26S DiSEqC 1.X typical application circuit

Table 5. LNBH26S DiSEqC 1.x bill of material

6 I·C bus interface

6.1 Data validity

6.2 START and STOP condition

6.3 Byte format

6.4 Acknowledge

6.5 Transmission without acknowledge

Figure 7. Data validity on the I·C bus

Figure 8. Timing diagram of I·C bus

Figure 9. Acknowledge on the I·C bus

7 I·C interface protocol

7.1 Write mode transmission

Figure 10. Example of writing procedure starting with first data address 0x2

7.2 Read mode transmission

Figure 11. Example of reading procedure starting with first status address 0X0

7.3 Data registers

Table 6. DATA 1 (read/write register. Register address = 0X2)

Table 7. DATA 2 (read/write register. Register address = 0X3)

Table 8. DATA 3 (read/write register. Register address = 0X4)

Table 9. DATA 4 (read/write register. Register address = 0X5)

7.4 Status registers

Table 10. STATUS 1 (read register. Register address = 0X0)

Table 11. STATUS 2 (read register. Register address = 0X1)

8 Electrical characteristics

Table 12. Electrical characteristics of section A/B

8.1 Output voltage selection

Table 13. Output voltage selection table (Data1 register, write mode)

Table 14. I·C electrical characteristics

Table 15. Address pin characteristics

9 Package mechanical data

Table 16. QFN24L (4x4 mm) mechanical data

Figure 12. QFN24L (4x4 mm) package dimensions

Figure 13. QFN24L (4x4) footprint recommended data (mm)

10 Revision history

Table 17. Document revision history