Samsung SDRAM 256Mb E-die (x4, x8, x16) Data Sheet

Summary

Datasheet (Revision 1.3, August 2004) for Samsung 256Mb E-die SDRAM (K4S560432E x4, K4S560832E x8, K4S561632E x16 organizations) in 54-pin TSOP-II Pb-free RoHS-compliant package. Features JEDEC standard 3.3V operation, LVTTL compatible multiplexed addressing, four-bank architecture, MRS cycle with programmable CAS latency (2/3), burst length (1/2/4/8/full page), and burst type (sequential/interleave). Supports burst read single-bit write, DQM/LDQM/UDQM data masking, auto refresh and self refresh

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SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM

256Mb E-die SDRAM Specification 54 TSOP-II with Pb-Free

(Ro HS compliant)

Revision 1.3 August 2004

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

Page Summary Contents For Samsung SDRAM 256Mb E-die (x4, x8, x16) Data Sheet

Page 1 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 256Mb E-die SDRAM Specification 54 TSOP-II with Pb-Free (Ro HS compliant) Revision 1.3 August 2004 * Samsung Electronics reserves the right to change product...

Page 2 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM Revision History Revision 1.0 (May. 2003) - First generation for Pb_free products Revision 1.1 (August. 2003) - Corrected typo in Page #8, 9 Revision 1.2 (Ma...

Page 3 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed addre...

Page 4 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM Package Physical Dimension 0.25 TYP 0.010 22.62 MAX 0.891 22.22 ± 0.10 0.21 ± 0.05 1.00 ± 0.10 1.20 MAX0.039 MAX 0.004 0. 3± 0. +0.10 0.05 0.71 0.30 -0.05 0....

Page 5 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM FUNCTIONAL BLOCK DIAGRAM I/O ontrol utput B uffer ense A LWE Data Input Register Bank Select Column Decoder ow ecoder ol. B uffer Latency & Burst Length ...

Page 6 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM PIN CONFIGURATION (Top view) x16 x8 x4 x16x8x4 VDD VDD VDD VSS VSS VSS DQ0 DQ0 N.C N.C DQ7 DQ15 VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ DQ1 N.C N.C N.C N.C DQ14 DQ2 DQ...

Page 7 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 Voltage on VDD supply relative to Vss VDD, VDDQ ...

Page 8 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Version Parameter Symbol Test Condition Unit Note Burst ...

Page 9 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Version Parameter Symbol Test Condition Unit Note Burst len...

Page 10 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 Input timing measurement reference le...

Page 11 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol Unit Note Min Max Min Max CAS latency=3 7.5 CLK cycle time t CC ns CAS l...

Page 12 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM IBIS SPECIFICATION 66MHz and 100MHz/133MHz Pull-up IOH Characteristics (Pull-up) 100MHz 100MHz 66MHz Voltage 133MHz 133MHz Min Max -100 Voltage IOH Min (100M...

Page 13 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM Minimum VDD clamp current VDD Clamp @ CLK, CKE, CS, DQM & DQ (Referenced to VDD) VDD (V) I (m A) 0.0 0.0 0.2 0.0 0.4 0.0 Voltage Minimum VSS clamp curren...

Page 14 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don't care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP Note Register Mode register set ...

Manual Details

Brand	Samsung
Pages	14
File Size	212.06 KB
Published	June 16, 2026

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Frequently Asked Questions

What power supply specifications does this SDRAM utilize?

It requires a JEDEC standard 3.3V power supply and is LVTTL compatible.

How often must the device refresh its memory contents?

The auto/self-refresh function maintains data with a 64ms refresh period (8K Cycle).

When are all inputs sampled relative to the system clock?

All inputs are sampled precisely at the positive going edge of the system clock.