Motorola MCM67J618B Data Sheet

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SEMICONDUCTOR TECHNICAL DATA by MCM67J618B/D

MCM67J618B

Product Preview 64K x 18 Bit Burst RAM Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67J618B is a 1,179,648 bit synchronous static random access

memory designed to provide a burstable, high–performance, secondary cache FN PACKAGE for the i486 and Pentium microprocessors. It is organized as 65,536 words PLASTIC CASE 778–02

of 18 bits, fabricated with Motorola’s high–performance silicon–gate Bi CMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Syn-

PIN NAMES

chronous design allows precise cycle control with the use of an external clock (K).

Bi CMOS circuitry reduces the overall power consumption of the integrated func- A0 – A15 Address Inputs. . . . . . . . . . . . . . . .

tions for greater reliability. Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADV Burst Address Advance. . . . . . . . . . . .

Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except

LW Lower Byte Write Enable. . . . . . . . . . . .

output enable (G) are clock (K) controlled through positive–edge–triggered non-

UW Upper Byte Write Enable. . . . . . . . . . . .

inverting registers.

ADSC Controller Address Status. . . . . . . . .

This device contains output registers for pipeline operations. At the rising edge

ADSP Processor Address Status. . . . . . . . .

of K, the RAM provides the output data from the previous cycle.

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

Output enable (G) is asynchronous for maximum system design flexibility. Output Enable. . . . . . . . . . . . . . . . . . . . . . Burst can be initiated with either address status processor (ADSP) or address DQ0 – DQ17 Data Input/Output. . . . . . . . . .

status cache controller (ADSC) input pins. Subsequent burst addresses can be VCC 5 V Power Supply. . . . . . . . . . . . . . . . generated internally by the MCM67J618B (burst sequence imitates that of the VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . .

i486) and controlled by the burst address advance (ADV) input pin. The following

All power supply and ground pins must be

pages provide more detailed information on burst controls. A6

connected for proper operation of the device.

Write cycles are internally self–timed and are initiated by the rising edge of the A7

clock (K) input. This feature eliminates complex off–chip write pulse generation A3 A2

and provides increased flexibility for incoming signals.

A1 LW

Dual write enables (LW and UW) are provided to allow individually writeable PIN ASSIGNMENT

A0 SC

bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17

SA5 AD SP

(the upper bits).

This device is ideally suited for systems that require wide data bus widths and

cache memory. See Figure 2 for applications information.

A1 GAD

8DQ9 DQ8

Single 5 V ± 5% Power Supply A1 A8

DQ10 DQ7

Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz A1 A9

VCC DQ6

Byte Writeable via Dual Write Enables VSS VCC Internal Input Registers (Address, Data, Control) DQ11 VSS DQ12 DQ5

Output Registers for Pipelined Applications

DQ13 DQ4

Internally Self–Timed Write Cycle

DQ14 DQ3

ADSP, ADSC, and ADV Burst Control Pins

VSS DQ2

Asynchronous Output Enable Controlled Three–State Outputs VCC

Common Data Inputs and Data Outputs DQ15 VCC

3.3 V I/O Compatible DQ16 DQ1 DQ17 DQ0

High Board Density 52–Lead PLCC Package ADSP Disabled with Chip Enable (E) — Supports Address Pipelining

Burst RAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA FAST SRAM  Motorola, Inc. 1996 MCM67J618B