Motorola MCM67B618A Data Sheet

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SEMICONDUCTOR TECHNICAL DATA by MCM67B618A/D

MCM67B618A

64K x 18 Bit Burst RAM Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67B618A is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors. It is organized as 65,536 words

FN PACKAGE

of 18 bits. The device integrates input registers, a 2–bit counter, high speed

PLASTIC

SRAM, and high drive capability outputs onto a single monolithic circuit for re-

CASE 778–02

duced parts count implementation of cache data RAM applications. Synchro- nous design allows precise cycle control with the use of an external clock (K). Bi CMOS circuitry reduces the overall power consumption of the integrated func-

PIN ASSIGNMENTS

tions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge– triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or

8DQ9 DQ8

address status cache controller (ADSC) input pins. Subsequent burst

DQ10 DQ7

addresses can be generated internally by the MCM67B618A (burst

VCC DQ6

sequence imitates that of the i486 and Pentium) and controlled by the burst

VSS VCC

address advance (ADV) input pin. The following pages provide more de-

DQ11 VSS

tailed information on burst controls.

DQ12 DQ5

Write cycles are internally self–timed and are initiated by the rising edge

DQ13 DQ4

of the clock (K) input. This feature eliminates complex off–chip write pulse

DQ14 DQ3

generation and provides increased flexibility for incoming signals.

VSS DQ2

Dual write enables (LW and UW) are provided to allow individually write- VCC

able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ15 VCC

DQ9 – DQ17 (the upper bits). DQ16 DQ1

This device is ideally suited for systems that require wide data bus DQ17 DQ0

widths and cache memory. See Figure 2 for applications information.

A1 LW Single 5 V ± 5% Power Supply A0 AD SC Fast Access Times: 9/10/12 ns Max SA5 AD SP AD

Byte Writeable via Dual Write Enables

A1 PIN NAMES

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle A0 – A15 Address Inputs. . . . . . . . . . . . . . . .

Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADSP, ADSC, and ADV Burst Control Pins A1 A9

ADV Burst Address Advance. . . . . . . . . . . .

Asynchronous Output Enable Controlled Three–State Outputs A1 A1

LW Lower Byte Write Enable. . . . . . . . . . . .

Common Data Inputs and Data Outputs

UW Upper Byte Write Enable. . . . . . . . . . . .

3.3 V I/O Compatible ADSC Controller Address Status. . . . . . . . .

High Board Density 52–Lead PLCC Package ADSP Processor Address Status. . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . . Output Enable. . . . . . . . . . . . . . . . . . . . . .

DQ0 – DQ17 Data Input/Output. . . . . . . . . . VCC 5 V Power Supply. . . . . . . . . . . . . . . . VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . NC No Connection. . . . . . . . . . . . . . . . . . . . .

All power supply and ground pins must be connected for proper operation of the device.

Burst RAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp.

REV 2 11/5/96

MOTOROLA FAST SRAM  Motorola, Inc. 1996 MCM67B618A