MOTOROLA MCM64PC32 MCM64PC64 DATA SHEET
Summary
These high-performance, burstable L2 cache modules are engineered for enhancing Pentium microprocessors within systems utilizing Intel’s Triton II chip set. Available in a standard 160-pin card edge format, these MCM modules provide critical storage functions via advanced BurstRAM technology (32K x 64 bits or 64K x 64 bits). This comprehensive guide serves as the technical resource for hardware engineers and system designers, detailing every aspect of implementation—including detailed pin assignments (A3-A18), timing diagrams, electrical specifications, and necessary signal integration points.
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SEMICONDUCTOR TECHNICAL DATA by MCM64PC32/D
MCM64PC32
Advance Information
MCM64PC64
256K/512K Pipelined Burst RAM Secondary Cache Module 160–LEAD CARD EDGE
CASE TBD, TOP VIEW
for Pentium The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 Burst RAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the Burst RAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache control. Pentium–Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled with Ex All Cache Data and Tag I/Os are TTL Compatible Three State Outputs Byte Write Capability Fast Module Clock Rate: 66 MHz Fast SRAM Access Times:15 ns for Tag RAM
8 ns for Data RAMs
One–Cycle Deselect Data RAMs Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes Single 3.3 V +10%, – 5% Power Supply Burndy Connector, Part Number: CELP2X80SC3Z48 Intel COAST 3.0 Option III Compliant Burst Order Select (BOSEL) Option
Burst RAM is a trademark of Motorola. Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA FAST SRAM Motorola, Inc. 1996 MCM64PC32•MCM64PC64
Page Summary Contents For MOTOROLA MCM64PC32 MCM64PC64 DATA SHEET
Manual Details
| Brand | Motorola |
|---|---|
| Pages | 16 |
| File Size | 180.65 KB |
| Published | May 30, 2026 |
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Frequently Asked Questions
What is the primary function of this memory module?
It provides a burstable, high performance, L2 cache for Pentium microprocessors paired with Intel’s Triton II chip set.
What voltage supply does the module require?
The unit requires a single 3.3 V (+10%, –5%) power supply.
What are the key operational timings?
Fast SRAM access times are 15 ns for Tag RAM and 8 ns for Data RAMs, with a fast clock rate of 66 MHz.
How can burst operations be initiated?
Bursts can be started using either an Address Status Processor (ADSP) or Cache Address Status (CADS).