MOTOROLA MC92303 Data Sheet User Guide
Summary
This high-performance digital demodulator is specialized for processing QPSK/BPSK signals in robust DVB compliant Digital TV set-top systems. Featuring automatic gain control, variable modulation rates up to 30 MBaud, and advanced signal tracking, it reliably extracts desired signals even with significant frequency offsets and adjacent channel interference. The technical documentation provides complete details on integration—including block diagrams and programming specifications—making it an essential resource for engineers building professional-grade broadcast reception systems.
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MOTOROLA Current [email protected]/ADC
SEMICONDUCTOR TECHNICAL DATA
MC92303
Product Brief QPSK/BPSK DIGITAL DEMODULATOR
RESET CLK
The MC92303 is a coherent digital demodulator for QPSK and BPSK modulated
I,Q[5:0] VCO
signals utilized in Digital-TV applications according to the EBU defined DVB transmis-
CLK_VCO AGC
sion standard for satellite Set-Top systems or similar. The MC92303 contains all the
FORMAT
functionality required to lock onto signals with frequency offsets as large as the baud
Q_soft[2:0]
rate and extract the desired signal from a frequency band with adjacent channel inter-
I_soft[2:0]
ference and other undesirable signals.
SDA SADR[6:0]
Feature Summary
DVB compliant QPSK/BPSK Coherent Demodulator Variable Modulation Rate up to 30 MBaud to work with all present European DVB Channels Selectable Input Format (Offset Binary/2’s Complement)
Ordering Information
DC Offset Removal, I/Q-swapping and Input Format Selection in one block Decimation Filters for Oversampling Ratios of 2/T, 3/T, 4/T, 6/T, 8/T, 12/T and 16/T
Device Package
Half Nyquist Baseband Filters (α=0.35) Internal Numerically Controlled Oscillator (NCO)
MC92303BT 160QFP
Automatic Gain Control (AGC) provided to analog front-end Automatic Frequency Control (AFC) to ±Rs (Symbol Rate) Clock Synchronization with 1-Bit Σ∆-Converter Output for ADC control Programmable Second Order Loop Filters for Carrier Recovery and AGC 3-bit Soft Decision output per Symbol with selectable format (Offset Binary/2’s Complement/Sign Magnitude) Programmable Sampling Rates of the Digital Sigma-Delta Converters < 0.5 d B Implementation Loss from theory I2C Programmable Interface 0.5µ CMOS Process at 3.3V
AGC AFC / Clock
AGC Σ∆ Ext. Clkref. Σ∆ VCO
Loop Filter Synchron.
Control Control
DC- Complex Decimation Half Nyquist I_soft
8/3 Bit Mapper
Removal Multiplier Q_soft
Filter Filter
Data Estimator
Digital AGC
cosΘ sinΘ
SDA False Lock Detector
I2C Sweep /
NCO Carrier
Interface
SADR Loop Filter Phase Lock Detector
Parameters
Figure 1. QPSK/BPSK Demodulator Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA, INC. 1997 4/10/97
Page Summary Contents For MOTOROLA MC92303 Data Sheet User Guide
Manual Details
| Brand | Motorola |
|---|---|
| Pages | 3 |
| File Size | 25.72 KB |
| Published | June 04, 2026 |
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Frequently Asked Questions
What modulation signals does the MC92303 process?
It functions as a coherent digital demodulator for QPSK and BPSK modulated I,Q VCO signals.
Can this device support various transmission standards?
Yes, it features variable modulation rates up to 30 MBaud, making it compatible with European DVB Channels.
How is the MC92303 controlled or configured?
It is a slaved device that must be controlled via an I²C interface for clock and register operations.
Are there any restrictions on product usage?
The product is not designed, intended, or authorized for use in surgical implants or life-sustaining applications.