LINEAR LTC4312 Technical Specifications User Guide

design features

2-Channel and 4-Channel Pin-Selectable I2C Multiplexer Features High Noise Margin, Capacitance Buffering, Level Translation and Stuck Bus Recovery Rajesh Venugopal

The inherent simplicity of I2C and SMBus 2-wire protocols The buffers provide capacitance isola- tion between the upstream bus and the

has made them a popular choice for communicating vital

downstream buses, allowing for parti-

information in large systems. Both standards employ

tioning of the bus capacitance. In single

simple open-drain pull-down drivers with resistive or

supply systems, the buffers regulate the

current source pull-ups. Nevertheless, several practical

bus up to 0.33 • VCC, providing a large

problems arise as systems grow in complexity. logic low noise margin. Rise time accel-

erators (RTAs) of appropriate strength

The first problem with large systems is buffers address these issues with a num-

can be activated to overcome bus capaci-

that devices with hard-wired I2C addresses ber of powerful features (see Table 1).

tance limitations, reduce rise time and

require address expansion to prevent Since these two devices share the same

allow for higher switching frequencies

conflicts. Second, noise causes glitches that features, except for the number of chan-

even when operating with heavy loads.

can be interpreted as legitimate clock or nels, this article focuses on the LTC4314. data transitions, compromising data reli- The LTC4314 is compatible with the

An upstream I2C bus (SDAIN, SCLIN) can be

ability. Third, I2C devices can cause the bus I2C standard and Fast Mode, SMBus and

connected to any combination of down-

to stick low. Finally, timing specifications PMBus specifications. Stuck bus recovery

stream buses through the LTC4314’s bus

are increasingly difficult to meet, and clock circuitry disconnects the upstream bus

buffers and multiplexer switches by driv-

frequencies are limited by the equivalent from downstream buses when SDA and

ing the ENABLE pins of the desired output

bus capacitance, which increases with SCL have not been simultaneously high at

buses high. Multiple devices having the

system size and complexity. The LTC4312 least once in 45ms, freeing the upstream

same address can be placed on different

and LTC4314 pin-selectable 2-channel bus to resume communications. The recov-

buses and isolated using the ENABLE pins,

and 4-channel I2C multiplexers with bus ery circuitry also attempts to convince

thereby achieving address expansion.

Table 1. Key features of the LTC4312 and LTC4314

FEATURE BENEFITS

2- and 4-Pin Selectable • Maximum flexibility of bus configurations

Downstream Buses • Address expansion when used as a MUX

• Breaks up bus capacitance, which allows large I2C compliant systems to be built, by keeping the capacitance of

I2C Buffers

each section < 400p F

• High logic low noise margin up to 0.33 • VCC

Selectable VIL

• Selectable RTA Operating voltage range

Level Translation • Provides I2C communication between 1.5V, 1.8V, 2.5V, 3.3V and 5V buses

• Reduce rise time

Rise Time Accelerators

• Allow larger bus pull-up resistors for better noise margin

(RTAs)

• Selectable RTA pull-up current strength

Disconnection and Recovery • Free masters to resume upstream communications

from Stuck Bus • Generates up to to 16 clock pulses and a stop bit on the stuck buses to convince the stuck device to release high

October 2011 : LT Journal of Analog Innovation | 11