Intel Intersil ISL6324A Data Sheet
Summary
This manual provides comprehensive specifications for the ISL6324A, a high-efficiency monolithic dual PWM hybrid controller designed for modern processor core voltage regulation (AMD SVI/PVI). It ensures stable power delivery with precision up to ±0.5% accuracy and advanced features like adaptive phase alignment. Engineers can rely on this guide for detailed system integration, covering pinouts, electrical parameters, optimal PCB layout, and managing complex operational modes, making it essential for builders of sophisticated computing hardware.
Page 1 Text Content
ISL6324A
Hybrid SVI/PVI with I2C
Data Sheet March 23, 2009 FN6880.0
Monolithic Dual PWM Hybrid Controller Features Powering AMD SVI Split-Plane and PVI
Processor Core Voltage Regulator Features
Uniplane Processors
Configuration Flexibility
The ISL6324A dual PWM controller delivers high efficiency
2-Phase Operation with Internal Drivers
and tight regulation from two synchronous buck DC/DC
3- or 4-Phase Operation with External PWM Drivers
converters. The ISL6324A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel Parallel VID (6-bit) Interface Inputs for PVI Mode
VID interface (PVI) or a serial VID interface (SVI). The dual PSI_L Support via Phase Shedding output ISL6324A features a multi-phase controller to support
Differential Remote Voltage Sensing
uniplane VDD core voltage and a single phase controller to
Optimal Processor Core Voltage Transient Response
power the Northbridge (VDDNB) in SVI mode. Only the
Adaptive Phase Alignment (APA)
multi-phase controller is active in PVI mode to support uniplane VDD only processors. Active Pulse Positioning Modulation
Processor Core Voltage Regulator and North Bridge
A precision uniplane core voltage regulation system is provided
Voltage Regulator Shared Features
by a 2-to-4-phase PWM voltage regulator (VR) controller. The integration of two power MOSFET drivers, adding flexibility in Precision Voltage Regulation: ±0.5% System Accuracy
layout, reduce the number of external components in the multi- Over-Temperature
phase section. A single phase PWM controller with integrated Two Wire, AMD Compliant Serial VID Interface Inputs for
driver provides a second precision voltage regulation system SVI Mode
for the North Bridge portion of the processor. This monolithic, I2C Interface dual controller with integrated driver solution provides a cost
Voltage Margining, OVP and PGOOD Trip Levels
and space saving power management solution.
Enhanced PSI_L State Control
For applications which benefit from load line programming to
Fully Differential, Continuous DCR Current Sensing
reduce bulk output capacitors, the ISL6324A features output
Accurate Load Line Programming
voltage droop. The multi-phase portion also includes
Precision Channel Current Balancing for Core
advanced control loop features for optimal transient response to load application and removal. One of these features is Overcurrent Protection highly accurate, fully differential, continuous DCR current
Multi-tiered Overvoltage Protection
sensing for load line programming and channel current
Variable Gate Drive Bias: 5V to 12V
balance. Dual edge modulation is another unique feature,
Simultaneous Digital Soft-Start of Both Outputs
allowing for quicker initial response to high di/dt load transients. Selectable Switching Frequency up to 1MHz
Pb-Free (Ro HS Compliant)
The ISL6324A supports Power Savings Mode by dropping phases when the PSI_L bit is set. The number of phases
Ordering Information
that the ISL6324A will drop to is programmable through an
PART TEMP.
I2C interface. The number of PWM cycles between both
NUMBER PART RANGE PACKAGE PKG.
dropping phases when entering Power Savings Mode and
(Note) MARKING (°C) (Pb-free) DWG. #
adding phases when exiting Power Savings Mode is also
ISL6324ACRZ* ISL6324A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
programmable through the I2C interface.
ISL6324AIRZ* ISL6324A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
The ISL6324A I2C interface also allows independent
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
programmable output voltage offset for both the Core and
reel specifications.
North Bridge regulators. The I2C interface can also be used NOTE: These Intersil Pb-free plastic packaged products employ
to set the PGOOD and OVP trip levels for both regulators as special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is
well.
Ro HS compliant and compatible with both Sn Pb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Page Summary Contents For Intel Intersil ISL6324A Data Sheet
Manual Details
| Brand | Intel |
|---|---|
| Pages | 39 |
| File Size | 864.91 KB |
| Published | May 29, 2026 |
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Frequently Asked Questions
How does the ISL6324A handle different processor voltage modes?
It provides hybrid power control, managing processors that utilize either a 6-bit parallel VID interface (PVI) or a serial VID interface (SVI).
What advanced features improve load transient response time?
Features like Active Pulse Positioning Modulation and fully differential DCR current sensing help maintain voltage accuracy and reduce droop during sudden load changes.
Does the device support different soldering requirements?
Yes, it is RoHS compliant, using a termination finish compatible with both SnPb and modern Pb-free soldering operations.
How can I program the power consumption for light loads?
The ISL6324A supports Power Savings Mode by dropping phases when the PSI_L bit is set, a function adjustable through the IC interface.