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Intel Silicon Intersil ISL6323B Data Sheet

Summary

This monolithic dual PWM hybrid controller is engineered for high-efficiency power management in systems utilizing AMD SVI/PVI split-plane processors. It delivers precision core voltage regulation through flexible 2- or 4-phase operation, ensuring optimal performance and component integration. This manual provides detailed technical specifications, operating guidelines, key features (like continuous DCR sensing and improved transient response), pinouts, and compliance information crucial for electronic hardware designers developing high-performance computing platforms.

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ISL6323B

March 23, 2009 FN6879.0Data Sheet

Monolithic Dual PWM Hybrid Controller Features Powering AMD SVI Split-Plane and PVI

Processor Core Voltage Via Integrated Multi-Phase

Uniplane Processors Power Conversion

Configuration Flexibility

The ISL6323B dual PWM controller delivers high efficiency

2-Phase Operation with Internal Drivers

and tight regulation from two synchronous buck DC/DC

3- or 4-Phase Operation with External PWM Drivers

converters. The ISL6323B supports hybrid power control of AMD processors which operate from either a 6-bit parallel PSI_L Support with Phase Shedding for Improved VID interface (PVI) or a serial VID interface (SVI). The dual Efficiency at Light Load output ISL6323B features a multi-phase controller to support

Serial VID Interface Inputs

uniplane VDD core voltage and a single phase controller to

Two Wire, Clock and Data, Bus

power the Northbridge (VDDNB) in SVI mode. Only the

Conforms to AMD SVI Specifications

multi-phase controller is active in PVI mode to support

Parallel VID Interface Inputs

uniplane VDD only processors.

6-bit VID input

A precision uniplane core voltage regulation system is

0.775V to 1.55V in 25m V Steps

provided by a two-to-four-phase PWM voltage regulator (VR)

0.375V to 0.7625V in 12.5m V Steps

controller. The integration of two power MOSFET drivers,

Precision Core Voltage Regulation

adding flexibility in layout, reduce the number of external

Differential Remote Voltage Sensing

components in the multi-phase section. A single phase PWM

±0.6% System Accuracy Over-Temperature

controller with integrated driver provides a second precision

Adjustable Reference-Voltage Offset

voltage regulation system for the North Bridge portion of the

processor. This monolithic, dual controller with integrated Optimal Processor Core Voltage Transient Response driver solution provides a cost and space saving power Adaptive Phase Alignment (APA) management solution. Active Pulse Positioning Modulation Fully Differential, Continuous DCR Current Sensing

For applications which benefit from load line programming to

Accurate Load Line Programming

reduce bulk output capacitors, the ISL6323B features output

Precision Channel Current Balancing

voltage droop. The multi-phase portion also includes advanced control loop features for optimal transient Variable Gate Drive Bias: 5V to 12V response to load apply and removal. One of these features

Overcurrent Protection

is highly accurate, fully differential, continuous DCR current

Multi-tiered Overvoltage Protection

sensing for load line programming and channel current balance. Dual edge modulation is another unique feature, Selectable Switching Frequency up to 1MHz allowing for quicker initial response to high di/dt load

Simultaneous Digital Soft-Start of Both Outputs

transients.

Processor North Bridge Voltage Via Single Phase

The ISL6323B supports Power Savings Mode by dropping Power Conversion the number of phases to two when the PSI_L bit is set.

Precision Voltage Regulation Ordering Information Differential Remote Voltage Sensing ±0.6% System Accuracy Over Temperature

TEMP. PART NUMBER PART RANGE PACKAGE PKG. Serial VID Interface Inputs (Note) MARKING (°C) (Pb-free) DWG. #

Two Wire, Clock and Data, Bus

ISL6323BCRZ* ISL6323B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 Conforms to AMD SVI Specifications ISL6323BIRZ* ISL6323B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7

Overcurrent Protection

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel

Continuous DCR Current Sensing

specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Variable Gate Drive Bias: 5V to 12V Pb-free material sets, molding compounds/die attach materials, and

Simultaneous Digital Soft-Start of Both Outputs

100% matte tin plate plus anneal (e3 termination finish, which is Ro HS compliant and compatible with both Sn Pb and Pb-free soldering

Selectable Switching Frequency up to 1MHz

operations). Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of Pb-Free (Ro HS Compliant)

IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2009. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Page Summary Contents For Intel Silicon Intersil ISL6323B Data Sheet

Page 1 ISL6323B March 23, 2009 FN6879.0Data Sheet Monolithic Dual PWM Hybrid Controller Features Powering AMD SVI Split-Plane and PVI Processor Core Voltage Via Integrated Multi-Phase Uniplane Processors Pow...
Page 2 ISL6323B Pinout ISL6323B (48 LD QFN) TOP VIEW FB_NB PWM4 ISEN_NB+ PWM3 RGND_NB VS EN PWROK P_ VID0/VFIXEN FS PHASE1 IS EN _N VC UGATE1 IS EN 4+ VID1/SEL SE BOOT1 IS EN 4- VID2/SVD FB IS EN 3+ VID3/SVC...
Page 3 ISL6323B Controller Block Diagram RGND_NB FB_NB COMP_NB NB_REF BOOT_NB UGATE_NB MOSFET ISEN_NB+ UV OV DRIVER CURRENT LOGIC PHASE_NB LOGIC SENSE RAMP ISEN_NB- LGATE_NB VDDPWRGD EN_12V PVCC_NB APAAPA NB...
Page 4 ISL6323B Typical Application - SVI Mode FB VSEN COMP BOOT1 ISEN3+ BOOT1 ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 LGATE1 LGATE1 PWM1 APA PGND ISEN1- ISEN1+ ISL6614 +12V +5V PVCC1_2 +12V VCC VCC PVCC BOO...
Page 5 ISL6323B Typical Application - PVI Mode FB VSEN COMP BOOT1 BOOT1 ISEN3+ ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 LGATE1 LGATE1 APA PGND ISEN1- ISEN1+ ISL6614 +12V PVCC1_2 VCC VCC BOOT2 BOOT2 OFS UGATE2...
Page 6 ISL6323B Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.2V Thermal Resistance θJA (°C/W) θJC (°C/W) Supply Voltage (PVCC)...
Page 7 ISL6323B Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature...
Page 8 ISL6323B Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature...
Page 9 ISL6323B Timing Diagram t PDHUGATE t RUGATE t FUGATE UGATE LGATE t FLGATE t RLGATE t PDHLGATE Functional Pin Description VID5 This pin is active only when the ISL6323B is in PVI mode. VID1/SEL When VI...
Page 10 ISL6323B when the POR-trip point of the external driver is reached, the BOOT1 and BOOT2 voltage at this pin meets the above mentioned threshold level. These pins provide the bias voltage for the corre...
Page 11 ISL6323B ISEN_NB-, ISEN_NB+ channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the These pins are used for differentially sensing the Nor...
Page 12 ISL6323B equivalent series resistance (ESR), and inductor ripple Positioning (APP) modulator is that the PWM signal has the current. Reducing the inductor ripple current allows the ability to turn on ...
Page 13 ISL6323B EXTERNAL CIRCUIT ISL6323B INTERNAL CIRCUIT CAPA RAPA VAPA,TRIP SWITCHING PERIOD TO APA PASS CIRCUITRY FILTER IL ERROR AMPLIFIER FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION The APA trip level...
Page 14 ISL6323B will program all the effective internal RISEN resistors to the VIN ILn same value. UGATE(n) Channel-Current Balance MOSFET DCRL VOUT One important benefit of multi-phase operation is the ther...
Page 15 ISL6323B voltage on the VID1/SEL pin. When the EN pin is toggled TABLE 1. 6-BIT PARALLEL VID CODES (Continued) HIGH, the status of the VID1/SEL pin will latch the ISL6323B VID5 VID4 VID3 VID2 VID1 VID...
Page 16 ISL6323B PRE-PWROK METAL VID If the EN input falls below the enable falling threshold, the ISL6323B ramps the internal reference voltage down to near Typical motherboard start-up occurs with the VFIXE...
Page 17 ISL6323B SVI MODE In the event the core voltage plane, VDD, is commanded to power off by serial VID commands, the VDDPWRGD signal Once the controller has successfully soft-started and remains asserted...
Page 18 ISL6323B POWER SAVINGS MODE: PSI_L EXTERNAL CIRCUIT ISL6323B INTERNAL CIRCUIT Bit 7 of the Serial VID codes transmitted as part of the 8-bit FS data phase over the SVI bus is allocated for the PSI_L. ...
Page 19 ISL6323B Output-Voltage Offset Programming The ISL6323B allows the designer to accurately adjust the offset voltage by connecting a resistor, ROFS, from the OFS VOFS RFB pin to VCC or GND. When ROFS i...
Page 20 ISL6323B This VID-on-the-fly compensation network works by above the PHASE or the PHASE falls to less than +0.8V, the sourcing AC current into the FB node to offset the effects of LGATE is released to...
Page 21 ISL6323B Detect block, the external driver POR checking is supported only change if the EN signal is pulled low or after a POR by the Enable Comparator. reset of VCC. Enable Comparator Soft-Start The ...
Page 22 ISL6323B level that might cause damage to the load. The lower OUTPUT PRECHARGED MOSFETs remain driven ON until VDIFF falls below 400m V. ABOVE DAC LEVEL The ISL6323B will continue to protect the load ...
Page 23 ISL6323B Undervoltage Detection (if active) in a high-impedance state, and forces VDDPWRGD low. This turns off all of the upper and lower MOSFETs. The The undervoltage threshold is set at VDAC - 300m ...
Page 24 ISL6323B OVERCURRENT PROTECTION IN POWER SAVINGS the capability of the MOSFETs to dissipate heat, and the MODE availability and nature of heat sinking and air flow. While in Power Savings Mode, the OC...
Page 25 ISL6323B A third component involves the lower MOSFET reverse-recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the 1.4 lower-MOSFET body diode can recove...
Page 26 ISL6323B In Equations 28 and 29, PQg_Q1 is the total upper gate drive Inductor DCR Current Sensing Component power loss and PQg_Q2 is the total lower gate drive power Selection and RSET Value Calculat...
Page 27 ISL6323B 6. Calculate the values for R1 and R2 for Core. CASE 3 Equations 35 and 36 will allow for their computation. ICore MAX (EQ. 43) INBMAX DCRNB⋅ DCRCore⋅= R2Core (EQ. 35) R1Core R2Core In Case 3...
Page 28 ISL6323B Inductor DCR Current Sensing Component Fine Tuning VIN ILn UGATE(n) MOSFET DCRL VOUT DRIVER LGATE(n) INDUCTOR VL(s) VC(s) ITRAN ISL6323B INTERNAL CIRCUIT In FIGURE 21. TIME CONSTANT MISMATCH ...
Page 29 ISL6323B C2 (OPTIONAL) f0> Case 1: f0 VP-P C⋅⋅ CCRC RC RFB ----------------------------------------------------------⋅= 0.66 VIN⋅ 0.66 VIN⋅ VPP RFB f0⋅ ISL6323B Case 2: C⋅⋅ ESR⋅ VP-P π⋅( )⋅ f0 C⋅ R...
Page 30 ISL6323B pulsating voltage at the phase nodes. The output filter also ESR⋅ R1 RFB -------------------------------------------⋅= must provide the transient energy until the regulator can C⋅ ESR⋅– respo...
Page 31 ISL6323B transient, the capacitor voltage becomes slightly depleted. Input Capacitor Selection The output inductors must be capable of assuming the entire The input capacitors are responsible for sour...
Page 32 ISL6323B IN PU T- PA IT EN (I S/ Low capacitance, high-frequency ceramic capacitors are to the CORE and NB power trains it controls through the needed in addition to the input bulk capacitors to suppr...
Page 33 ISL6323B significantly reduce the possibility of shoot-through. It is also The sense traces that connect the R-C sense components to important to route each channels UGATE and PHASE traces each side o...
Page 34 ISL6323B CC RC CIN R3_2 FB VSEN CBOOT CBOOT BOOT1 R3_1C3 BOOT1 ISEN3+ ISEN3- UGATE1 UGATE1 PWM3 PHASE1 PHASE1 CAPA R1_1 C1 LGATE1 LGATE1 PGND ISEN1- ISEN1+ ISL6614 +12V V_CORE +5V PVCC1_2 +12V CFILTER...
Page 35 ISL6323B Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 PIN #1 INDEX AREA PIN 1 INDEX AREA TOP VIEW 48X 0 . 40± 0 . 1 BOTTOM VIEW SEE DETAIL "X" 0 . 9...

Manual Details

Brand Intel
Pages 35
File Size 836.69 KB
Published May 30, 2026
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Frequently Asked Questions

What voltage range is available for uniplane core voltage regulation?

The system supports 0.775V to 1.55V in precise 25mV steps.

How does this controller support different AMD processor types?

It can handle both a serial VID interface (SVI mode) and a parallel VID interface (PVI mode).

What specific precautions should be taken when handling the ISL6323B device?

These devices are sensitive to electrostatic discharge; proper IC Handling Procedures must be followed.