Intel Intersil 82C284 Data Sheet

Summary

This clock generator system is designed to provide comprehensive timing control and clock signal distribution for 80C286 processors. It manages the generation of primary system clocks, reset outputs, and synchronized READY signals from both asynchronous and synchronous sources. The manual offers detailed functional diagrams and pin descriptions, guiding engineers in implementing precise bus synchronization and frequency switching necessary for complex embedded hardware designs.

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82C284 Clock Generator and Ready Interface March 1997 for 80C286 Processors

Features Description Generates System Clock for 80C286 Processors The Intersil 82C284 is a clock generator/driver which

provides clock signals for 80C286 processors and support

Generates System Reset Output from Schmitt

components. It also contains logic to supply READY to the

Trigger Input

CPU from either asynchronous or synchronous sources and

Improved Hysteresis

synchronous RESET from an asynchronous input with hysteresis.

Uses Crystal or External Signal for Frequency Source Dynamically Switchable between Two Input

Ordering Information

Frequencies

Provides Local READY and MULTIBUS READY

PART NUMBER TEMP. RANGE PACKAGE NO.

Synchronization

CD82C284-12 0o C to +70o C 18 Ld CERDIP F18.3

Static CMOS Technology

ID82C284-10 -40o C to +85o C 18 Ld CERDIP F18.3

Single +5V Power Supply

ID82C284-12 -40o C to +85o C 18 Ld CERDIP F18.3

Available in 18 Lead Cer DIP Package

Pinout Functional Diagram

82C284 (CERDIP) TOP VIEW

RESET

ARDY VCC RES SRDY ARDYEN

SYNCHRONIZER

SRDYEN S1

READY S0 X1

XTAL X2 OSC

EFI NC

MUX CLK

F/C PCLK

X1 RESET

X2 RES

GND CLK

ARDYEN

SYNCHRONIZER

SRDYEN

READY LOGIC

SRDY READY

PCLK GENERATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2966.1

MULTIBUS is a patented Intel bus.

Page Summary Contents For Intel Intersil 82C284 Data Sheet

Page 1 82C284 Clock Generator and Ready Interface March 1997 for 80C286 Processors Features Description Generates System Clock for 80C286 Processors The Intersil 82C284 is a clock generator/driver which prov...

Page 2 Pin Description The following pin function descriptions are for the 82C284 clock generator. PIN SYMBOL NUMBER TYPE DESCRIPTION CLK SYSTEM CLOCK: the signal used by the processor and support devices wh...

Page 3 Functional Description 2) When switching CLK frequency sources, there is a max- imum transition latency of 2.5 clock cycles of the fre- Introduction quency being switched to, from the time CLK freezes...

Page 4 FIGURE 1B. F/C SWITCHED FROM LOW (USING THE CRYSTAL INPUT X1) TO HIGH (USING THE EFI INPUT) FIGURE 1. DYNAMICALLY SWITCHING THE F/C PIN The 82C284 provides a second clock output, PCLK, for periph- CLK...

Page 5 LOW to HIGH input transition voltage. As long as the slope of the RES input voltage remains in the same direction (increas- X1 CLK CLK ing or decreasing) around the RES input transition voltage, the R...

Page 6 TS TC TC T1 VIH ARDYEN SRDYEN READY FIGURE 5. SYNCHRONOUS READY OPERATION TS TC TC T1 VIH SRDYEN ARDYEN READY FIGURE 6. ASYNCHRONOUS READY OPERATION

Page 7 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance θJA (o C/W) θJC (o C/W) Input, Output or I...

Page 8 AC Electrical Specifications TA = 0o C to +70o C (CD82C284); VCC = 5V ±10% (Continued) TA = -40o C to +85o C (l D82C284) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated...

Page 9 UNTESTED SPECIFICATIONS (Continued) 10MHz 12.5MHz SYMBOL PARAMETER MAX MIN MAX UNITS CONDl TIONS (NOTE 1)MIN t19 CLK Rise Time ns 1.0V to 3.6V, CL = 100p F t20 CLK Fall Time ns 3.6V to 1.0V, CL = 100p...

Page 10 Waveforms t15Bt19 NOTE: 1. The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown. FIGURE 9. CLK AS A FUNCTION OF EFI t13 NOTE RESET DEPENDS ON STATE OF P...

Page 11 Waveforms (Continued) NOTE: 1. This is an asynchronous input. The setup and hold times are required to guarantee the response shown. FIGURE 12. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAM...

Manual Details

Brand	Intel
Pages	11
File Size	72.19 KB
Published	May 30, 2026

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Frequently Asked Questions

What is the purpose of this clock generator?

It generates system clock signals for 80C286 processors and supports multiple ready signal outputs.

How can I change the CLK frequency while running?

Use the F/C pin. Setting it HIGH allows the EFI input to drive CLK, enabling dynamic switching between frequencies.

What is the PCLK output?

PCLK provides a 50% duty cycle clock that is half the frequency of the main CLK signal. It will be in phase following the first bus cycle after processor reset.

Does the device handle system resets?

The active LOW RES input generates a robust system reset signal using a Schmitt trigger, which accepts asynchronous signals.