Fairchild FDC6321C User Manual
Summary
The DC6321C is a dual N & P channel logic-level enhancement mode MOSFET designed for efficient low-voltage load switching applications, particularly in simple 3V circuits. This advanced FET simplifies circuit design by replacing multiple digital transistors and eliminating the need for external bias resistors. The accompanying datasheet provides comprehensive electrical specifications, including absolute maximum ratings, dynamic characteristics, thermal profiles, and detailed usage guidelines necessary for precise integration into new electronic systems.
Page 1 Text Content
April 1999
FDC6321C Dual N & P Channel , Digital FET General Description Features These dual N & P Channel logic level enhancement mode N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V. high density process is especially tailored to minimize
Very low level gate drive requirements allowing direct
on-state resistance. This device has been designed
operation in 3 V circuits. VGS(th) < 1.0V.
especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias
Gate-Source Zener for ESD ruggedness.
resistors are not required this dual digital FET can replace
>6k V Human Body Model
several digital transistors with different bias resistors.
Replace multiple dual NPN & PNP digital transistors.
SOT-23 Super SOTTM-8 SOIC-16SO-8
SOT-223Super SOTTM-6
Mark:.321
Super SOT -6TM
Absolute Maximum Ratings TA = 25o C unless other wise noted Symbol Parameter N-Channel P-Channel Units VDSS, VCC Drain-Source Voltage, Power Supply Voltage -25 VGSS, VIN Gate-Source Voltage, 8 -8 ID, IO Drain/Output Current - Continuous 0.68 -0.46
- Pulsed -1.5
PD Maximum Power Dissipation (Note 1a) 0.9
(Note 1b)
TJ,TSTG Operating and Storage Tempature Ranger -55 to 150 °C ESD Electrostatic Discharge Rating MIL-STD-883D k V
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) °C/W
© 1999 Fairchild Semiconductor Corporation FDC6321C.Rev B
Page Summary Contents For Fairchild FDC6321C User Manual
Manual Details
| Brand | Fairchild |
|---|---|
| Pages | 8 |
| File Size | 130.22 KB |
| Published | July 06, 2026 |
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Frequently Asked Questions
What voltage range is this device specifically designed for?
This dual digital FET is specifically designed for operation in 3V circuits and low voltage switching applications.
How robust is the component against static electricity?
The device offers ESD ruggedness rated by MIL-STD-883D, with a Human Body Model rating greater than 6 kV.
What are the thermal characteristics for mounting the FET?
The Junction-to-Case Thermal Resistance is 140 °C/W, and the Junction-to-Ambient Thermal Resistance is 60 °C/W.
Can this component be used in life support medical devices?
No, Fairchild's products are not authorized for use as critical components in life support devices or systems without explicit written approval.