Motorola MPC2104P MPC2105P User Guide
Summary
The MPC2104P and MPC2105P are secondary cache modules providing high-performance, burstable L2 cache for PowerPC 60x microprocessors operating within PReP/CHRP platforms. These units utilize advanced synchronous BurstRAM technology to accelerate system processing speed. This technical manual provides detailed specifications, pin assignments, and operational parameters necessary for engineers designing reliable, high-speed computing systems for PowerPC embedded applications requiring maximum data throughput.
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256KB/512KB Burst RAM Secondary Cache Modules for Power PC PRe P/CHRP Platforms The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the Power PC 60x microprocessor family in conformance with the Power PC Reference Platform (PRe P) and the Power PC Common Hardware Reference Platform (CHRP) specifications. The MPC2104P and MPC2105P utilize synchronous Burst RAMs. The MPC2104P module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 2104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid and dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internally to the Burst RAM by the CNTEN signal. Write cycles are internally self–timed and are initiated by the rising edge of the clock (CLKx) inputs. Writes are global with two inputs for reduced loading. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. Power PC–Style Burst Counter On Chip Pipeline Data I/O Plug and Pin Compatibility Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible Three State Outputs Buffered Addresses to Data RAMs for Reduced Loading Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 9 ns for Tag RAM Match
8 ns for Data RAM
Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes 178 Pin Card Edge Module Burndy Connector, Part Number: ELF178KSC–3Z50
Burst RAM is a trademark of Motorola. The Power PC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2 12/20/96
MOTOROLA FAST SRAM Motorola, Inc. 1996 MPC2104P•MPC2105P
Page Summary Contents For Motorola MPC2104P MPC2105P User Guide
Manual Details
| Brand | Motorola |
|---|---|
| Pages | 16 |
| File Size | 162.92 KB |
| Published | May 27, 2026 |
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Frequently Asked Questions
What PowerPC platforms are the MPC2104P and MPC2105P designed for?
These modules provide L2 cache for the PowerPC 60x microprocessor family, conforming to PReP and CHRP specifications.
What is a key compatibility feature of this module family?
The module family supports both 5 V and 3.3 V components, ensuring clear paths for lower voltage operation while being plug and pin compatible with each other.
What are the fast SRAM access times advertised?
Fast SRAM access promises up to 9 ns for Tag RAM match time and 8 ns for Data RAM match time.
Are all cache data and tag I/Os compatible with LVTTL?
Yes, all Cache Data and Tag I/Os are specified as being LVTTL (3.3 V) Compatible, ensuring reduced loading on the system.