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MAXIM MAX9173 Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe User Manual Data Sheet

Summary

The MAX9173 is a high-speed Quad LVDS Line Receiver designed for reliable data signal processing up to 500Mbps. It accepts four differential LVDS inputs and converts them to standardized LVCMOS/LVTTL outputs, simplifying professional PCB layout with its flow-through pinout and incorporating an 'in-path' fail-safe circuit. This device is essential for electronics designers building sophisticated equipment such as network switches, digital copiers, laser printers, and telecom systems that require high-integrity, low-noise signal handling conforming to ANSI TIA/EIA-644 standards.

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Page 1 Text Content

19-2595; Rev 0; 10/02

Quad LVDS Line Receiver with Flow-Through

Pinout and “In-Path” Fail-Safe

General Description Features

The MAX9173 quad low-voltage differential signaling Accepts LVDS and LVPECL Inputs (LVDS) line receiver is ideal for applications requiring

Fully Compatible with DS90LV048A

high data rates, low power, and low noise. The

Low 1.0m A (max) Disable Supply Current

MAX9173 is guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance In-Path Fail-Safe Circuitry media of approximately 100Ω. The transmission media

Flow-Through Pinout

can be printed circuit (PC) board traces or cables.

Simplifies PC Board Layout

The MAX9173 accepts four LVDS differential inputs and Reduces Crosstalk translates them to LVCMOS/LVTTL outputs. The

Guaranteed 500Mbps Data Rate

MAX9173 inputs are high impedance and require an

400ps Pulse Skew (max)

external termination resistor when used in a point-to- point connection. Conforms to ANSI TIA/EIA-644 LVDS Standard The device supports a wide common-mode input range High-Impedance LVDS Inputs when Powered-Off

of 0.05V to VCC - 0.05V, allowing for ground potential

Available in Tiny 3mm x 3mm QFN Package

differences and common-mode noise between the dri- ver and the receiver. A fail-safe feature sets the output

Ordering Information

high when the inputs are open, or when the inputs are undriven and shorted or undriven and parallel terminat-

PART TEMP RANGE PIN-PACKAGE

ed. The EN and EN inputs control the high-impedance

outputs. The enables are common to all four receivers. MAX9173EUE -40°C to +85°C 16 TSSOP

Inputs conform to the ANSI TIA/EIA-644 LVDS stan- MAX9173ESE -40°C to +85°C 16 SO dard. The flow-through pinout simplifies board layout

MAX9173ETE* -40°C to +85°C 16 Thin QFN-EP**

and reduces crosstalk by separating the LVDS inputs

and LVCMOS/LVTTL outputs. The MAX9173 operates *Future product. Contact factory for availability. **EP = Exposed pad.

from a single 3.3V supply, and is specified for opera- tion from -40°C to +85°C. Refer to the MAX9121/ MAX9122 data sheet for lower j itter quad LVDS

Typical Operating Circuit

receivers with parallel fail-safe. Refer to the MAX9123 data sheet for a quad LVDS line driver with flow- LVDS SIGNALS through pinout.

MAX9123 MAX9173

The device is available in 16-pin TSSOP, SO, and space-saving thin QFN packages.

Tx 100Ω Rx

Applications

Digital Copiers

Tx 100Ω Rx

Laser Printers Cellular Phone Base Stations

LVTTL/LVCMOS LVTTL/LVCMOS DATA INPUTS DATA OUTPUTS

Network Switches/Routers Backplane Interconnect

Tx 100Ω Rx

Clock Distribution LCD Displays Telecom Switching Equipment

Tx 100Ω Rx

Pin Configurations and Functional Diagram appear at end of

100Ω SHIELDED TWISTED CABLE OR MICROSTRIP BOARD TRACES

data sheet.

Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Page Summary Contents For MAXIM MAX9173 Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe User Manual Data Sheet

Page 1 19-2595; Rev 0; 10/02 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe General Description Features The MAX9173 quad low-voltage differential signaling Accepts LVDS and LVPECL ...
Page 2 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe ABSOLUTE MAXIMUM RATINGS VCC to GND ..........................................................-0.3V to +4.0V Junction Temperatu...
Page 3 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, CL = 15p F, |VID| = 0.2V, VCM = 1.2V, and TA = -40°C to +85°C. Typical value...
Page 4 OU TP UT OW OL TA GE (m V) OU TP UT HO RT -C IR CU IT UR RE NT (m A) SU PP LY UR RE NT (m A) Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Typical Operating Characteristics ...
Page 5 TR AN SI TI ON IM (p s) DI FF ER EN TI AL RO PA GA TI ON EL AY (n s) Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Typical Operating Characteristics (continued) DI FF ER EN ...
Page 6 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Pin Description NAME FUNCTION TSSOP/SO QFN IN1- Inverting Differential Receiver Input for Receiver 1 IN1+ Noninverting Differen...
Page 7 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Fail-Safe The MAX9173 fail-safe drives the receiver output high when the differential input is: Undriven and shorted Undriven a...
Page 8 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Termination inputs should be separated by 180° from the The MAX9173 requires an external termination resistor. LVTTL/LVCMOS out...
Page 9 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe DEVICE IN_- UNDER OUT_ GENERATOR EN EN 50Ω 1/4 MAX9173 CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR t PZL AND t PLZ ...
Page 10 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Pin Configurations TOP VIEW IN1- EN IN1+ OUT1 IN2+ OUT2 IN2+ OUT2 IN2- VCC IN2- MAX9173 VCC IN3- MAX9173 GND IN3- GND IN3+ OUT3...
Page 11 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest ...
Page 12 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For...
Page 13 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For...
Page 14 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For...

Manual Details

Brand QUAD
Pages 14
File Size 340.76 KB
Published May 29, 2026
57 views

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Frequently Asked Questions

What is the maximum guaranteed data rate of this receiver?

The MAX9173 is guaranteed to receive data at speeds up to 500Mbps.

Does the flow-through pinout simplify PCB design?

Yes, it simplifies PC Board Layout and helps reduce crosstalk.

Is an external termination resistor required for operation?

Yes, a 400ps Pulse Skew (max) external termination resistor is needed in point-to-point connections.

What does the 'In-Path' fail-safe circuit do?

It maintains safe output by detecting open, undriven/shorted, or parallel terminated inputs.