LINEAR TECHNOLOGY - 1 LTC1403 LTC1403A Data Sheet

LTC1403/LTC1403A

Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown

FEATURES DESCRIPTIO

2.8Msps Conversion Rate The LTC®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se- Low Power Dissipation: 14m W rial ADCs with differential inputs. The devices draw only 3V Single Supply Operation 4.7m A from a single 3V supply and come in a tiny 10-lead 2.5V Internal Bandgap Reference can be Overdriven MS package. A Sleep shutdown feature lowers power

-B IT AT CH

3-Wire Serial Interface consumption to 10µW. The combination of speed, low Sleep (10µW) Shutdown Mode power and tiny package makes the LTC1403/LTC1403A Nap (3m W) Shutdown Mode suitable for high speed, portable applications.

80d B Common Mode Rejection

The 80d B common mode rejection allows users to elimi-

0V to 2.5V Unipolar Input Range

nate ground loops and common mode noise by measuring

Tiny 10-Lead MS Package

signals differentially from the source. The devices convert 0V to 2.5V unipolar inputs differen-

APPLICATIO tially. The absolute voltage swing for +AIN and –AIN

extends from ground to the supply voltage.

Communications

Data Acquisition Systems The serial interface sends out the conversion results

Uninterrupted Power Supplies TH D, nd , S FD R, rd (d B) during the 16 clock cycles following CONV↑ for compat-

Multiphase Motor Control ibility with standard serial interfaces. If two additional Multiplexed Data Acquisition clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. , LTC and LT are registered trademarks of Linear Technology Corporation.

BLOCK DIAGRA

3V10µF 2nd, 3rd and SFDR vs Input Frequency

LTC1403A VDD –50

AIN +1 THREE- THD 2nd, SFDR

STATE

S & H 14-BIT ADC SERIAL SDO

OUTPUT

PORT –74

–80 VREF –86

2.5V TIMING

REFERENCE LOGIC

–104 1403A TA015 0.1

EXPOSED PAD FREQUENCY (MHz)

1403A TA02

sn1403a 1403afs