LINEAR Application Note 135 - User Guide

Application Note 135

April 2012

Implementing Robust PMBus System Software for the LTC3880 Nick Vergunst

INTRODUCTION commands because PMBus/SMBus provide timeouts to prevent bus hangups and optional packet error checking

The LTC®3880 is a dual output Poly Phase® step-down DC/DC

(PEC) to ensure data integrity.

controller with integrated digital power system manage-

ment. The LTC3880 can easily be controlled through a In general, a master device configured for I2C communi- PMBus interface, which builds upon I2C/IIC at speeds up cation is used for PMBus communication with little or no to 400k Hz. System telemetry data can be obtained quickly change to hardware or firmware. Repeated starts (restarts) and painlessly with simple polling functions. This exposes are not supported by all I2C controllers but are required for PMBus/SMBus reads. If a general purpose I2C controller

all important and critical information to the system devel-

is used, check that repeated starts are supported.

oper such as the voltage and current readings for the input and both outputs, temperature, fault conditions, general For a full description of the extensions and exceptions status information, and more. PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.1: Paragraph 5: Transport.

This application note discusses the design requirements in regards to implementing robust firmware capable of For a full description of the differences between SMBus

interacting with the LTC3880. and I2C, refer to System Management Bus (SMBus) Speci- fication Version 2.0: Appendix B—Differences Between SMBus and I2C.

DOCUMENT OVERVIEW This document is broad in scope. If you already feel comfort- Quick Overview of PMBus vs SMBus vs I2C able with I2C/SMBus/PMBus and the transaction structure

The power management bus (PMBus) protocol is built

for the command set, then you may wish to skip ahead to

upon the system management bus (SMBus) which builds

the Communicating Robustly with the LTC3880 section.

upon the 2-wire open drain communication interface inter- integrated circuit (I2C or IIC).

REFERENCE DESIGN OVERVIEW

PMBus dictates a maximum bus speed of 400k Hz and has The PMBus master design used in this application note built-in timeouts important for critical systems. Though is an off-the-shelf microcontroller (Microchip PIC32MX), clock stretching is fully PMBus compliant, it is not required but any microcontroller, FPGA, or other device with a with the LTC3880 if operating at bus speeds at or below programmable PMBus/I2C interface can be used. All the 100k Hz and the guidelines below are followed. Because code examples are written for the PIC32MX architecture, of the built-in timeouts, a minimum bus speed of 10k Hz but they are easily adapted to other target designs. exists for all PMBus devices. Some of the key differences between PMBus and SMBus PMBus vs SMBus vs I2C/IIC INTRODUCTION in relation to the low level bus are: • 400k Hz maximum bus speed vs 100k Hz SMBus limit

The power management bus (PMBus) 2-wire interface is

• Group protocol

an incremental extension of the system management bus

• Block reads up to 255 bytes in length vs 32 byte SMBus

(SMBus). SMBus is built upon I2C with some differences

limit

in timing, DC parameters, and protocol. The PMBus/

L, LT, LTC, LTM, Linear Technology, Poly Phase and the Linear logo are registered trademarks

SMBus protocols are more robust than simple I2C byte

and LTpower Play is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

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