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LINEAR AN48 Using LTC Op Amp Macromodels

Summary

This application note provides an essential guide for analog circuit designers utilizing macromodels and SPICE simulations. It discusses how modern simulation tools help achieve design feasibility, focusing specifically on maximizing performance with op-amp macromodels within advanced libraries. The manual covers critical topics such as model quality assessment, understanding the limitations of predictive analysis, and ensuring accurate results when designing complex circuits that require rigorous verification.

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Application Note 48 November 1991

Using the LTC Op Amp Macromodels Getting the Most from SPICE and the LTC Library

Walt Jung

INTRODUCTION

This application note is an overview discussion of the would not be taking place. However, all is not necessarily Linear Technology SPICE macromodel library. It assumes peaceful bliss for analog designs, and yes, we still need to little if any prior knowledge of this software library or its actually build breadboards to check out circuit designs in history. However, it does assume familiarity with both the the lab. The go-go project managers may say “Simulate it, analog simulation program SPICE (or one of its many we don’t have time to fool with the breadboard and hand- derivatives), and modern day op amps, including bipolar, built prototypes.” Rarely will this ramrod approach be a JFET, and MOSFET amplifier technologies. truly wise move, now or in the future, except in specialized circumstances.

Some Preliminary SPICE Facts of Life

While it is certainly true that we are in the age of comput-

In the past few years, SPICE simulations have really begun ers, and that they really do aid our tasks in many ways, that to capture a high level of attention on the part of analog is simply not enough for all cases. SPICE (or any simula- circuit designers. Perhaps this is due to more affordable tion tool) can only act upon the information fed into it to high performance computers, or perhaps the time for analyze a circuit. Model quality issues set aside for the simulation is now upon us. In any event, the bottom line is moment, can you honestly say that you have fully suffi- that IC vendors are now making macromodels for op amps cient characterization data for every single relevant con- available to their customers. nection point/load that your circuit will ever see? Do you

understand all of the parasitic issues it will face? If you can

For the analog circuit designer, there can be no better fate

say yes to all of these, then maybe all that you need is just

for simulations, viewing this situation in terms of which

a good op amp model, and SPICE. More likely, there will

model to use. Designers no longer need worry about

always be some uncertainties, so breadboarding will re-

whether the third party supplier’s model can really cut it.

main the only advisable choice for relatively complex

Speaking in terms of the ultimate potential, no one can

circuits, particularly those never built before.

know an actual part better than the people who designed and produced it, that is the original source IC vendor. The This then leaves a question of model quality and degree of only possible caveat to this scenario is that the vendor functionality to be answered. Are the presently available supplying an op amp model needs to fully understand not models enough? Just how far can they be trusted for the only the real part, but they must also understand SPICE types of simulations that are to be performed? Hopefully, and modeling issues. Without both types of understand- most of these answers will be more apparent by the end of ing firmly in place, the user can end up with a real part that this note, as it contains many different examples. Never- works well and a model which doesn’t. For such a case, theless, no IC vendor (or other model supplier) is likely to simulation will be of little value; simulation runs to verify ever stand up and say, “We guarantee this model when circuit performance won’t match the actual part’s bench used with simulator ABC, and the simulated performance performance. will be within X% of the actual part connected within a

corresponding circuit.”

Fortunately, this type of problem seems to be diminishing.

If this were not so, the rapid increase in attention to models and LTC are registered trademarks and LT is a trademark of Linear Technology Corporation.

AN48-1

Page Summary Contents For LINEAR AN48 Using LTC Op Amp Macromodels

Page 1 Application Note 48 November 1991 Using the LTC Op Amp Macromodels Getting the Most from SPICE and the LTC Library Walt Jung INTRODUCTION This application note is an overview discussion of the would n...
Page 2 Application Note 48 Forget it, SPICE simply doesn’t work that way, and likely So, perhaps the first thing to understand about SPICE op never will. What SPICE is good for is predictive analysis, amp ma...
Page 3 Application Note 48 RC1 RC2 30p F VB VC 4.6p F VA GCMVE GAVA R2 RO2 GBVB RE1 RE2 IEE CE RE RC GCV6 27.5E–6 1.6p F 7.3M 200µΩ 5k S VE 3.1 4–VEE NODE "0" (GND) IS DEFAULT COMMON IN SPICE.KEY E...
Page 4 Application Note 48 (IOS), output current limiting (ISC), output voltage limits presumption that the gain from the amplifier’s ± inputs to (VSAT ±), output resistance (ROUT), and power supply the diff...
Page 5 Application Note 48 remaining path of the model can be essentially the same, THE LTC APPROACH TO SPICE OP AMP with the basic design equations holding. For example, in MACROMODELS the case of a PFET ty...
Page 6 Application Note 48 IP VP RC1 RC2 CXC1 DSUB D3A RXC1 C2 Q1 Q2 GM1 GM2 VCL VCL R2 RO2 100k 100k VE DDM4 GCMVE GAVA GPLVP GNLVP GPLVP GBVB RB2 CIN RE1 RE2 DDM3 D1 VE VI D2 VN CE RE RCL IEE VN NOTES: 1) ...
Page 7 Application Note 48 RC1 RC2 RPLA RPLB RXC2 D3B RXC1 CXC2 C2 VC ECL OUT R2 RO2 RB1 GCM Q1 Q2 QM1 QM2 DDM2 RE1 RE2 RB2 CIN D4B RCL D4A RNLA RNLB NOTES: 1) INPUT ELEMENTS CIN, RB1/2, DDM1/2/3/4 WILL VARY...
Page 8 Application Note 48 C2 can be expanded from the original Boyle single capaci- limiter with two series diodes and a similar offset voltage tor, to more complex optional network(s). The LT1007 source fo...
Page 9 Application Note 48 without either limiter (for special cases). In fact, they can device uses bias current compensation, and the model be disabled for signal purposes very simply, by comment- accounts...
Page 10 Application Note 48 25.30 (m A) TIME (ms) V (V) LTAN48 • TA05 LTAN48 • TA06 Figure 5A. LT1007 Test F6: ISC (Open Loop, VS = ±15V) Figure 5B. LT1007 Test F7: VSAT (VS = ±15V) Vp(55) –Vp(50,51) –180 FRE...
Page 11 Application Note 48 output of (55), and the signal source is applied to node (2). ing data sheet photo. The test is a deceptively simple one, Unless otherwise specified, no SPICE option default as mos...
Page 12 Application Note 48 with the release of macromodels for the PNP input op Further discussion and performance examples of this amps LT1013 and LT1014.6 These models actually had specific model type are ...
Page 13 Application Note 48 IEE V– RE1 RE2 D3 QM1 QM2 RO1 RO2B DCM1 DCM2 R2 RO2A C1 GCM CE RE D1 RC1 RC2 EC D4 NOTES: 1. INPUT CLAMPING ELEMENTS RB1, RB2, DCM1, DCM2, VCMC WILL VARY 2. MICROPOWER DEVICES HAVE...
Page 14 Application Note 48 6.0 (m V) (m V) (V is V(55), and as noted, it is clamped at 0V/4V limits, and there is no phase reversal when the input is taken well below GND (maximum input sink current is 5V/10...
Page 15 Application Note 48 Junction FET input op amps make up an important part of LT1056 (a representative LTC PFET op amp) is shown in the overall field of op amps, as they are capable of both Listing 5. m...
Page 16 Application Note 48 V+ NOTE 3GOSIT V– RPLA RPLB RS1 RS2 PJ2 GA PJ1 D3B R2 RO2 GCM VE DCM3 DCM1 RD1 RD2 CS GCL DCM2DCM4 RNLA RNLB VCMC VCM2 NOTES: 1) SECTIONS SHOWN DOTTED OPTIONAL. 2) OUTPUT VOLTAGE/C...
Page 17 Application Note 48 industry standard parts such as the LF156-LF356 series, The remainder of this model (the output stage with en- the OP-15/OP-16 series, and the related duals. Since the hanced volta...
Page 18 Application Note 48 TIME ( s) LTAN48 • TA16 Figure 9A. LT1056 Test F1: Asymmetric Slew Rate V(2) –V(55) –(I (R1) –50E –12)IG (XU1. J1) V (V) V (V) V (V) IN IN IN LTAN48 • TA17 Figure 9B. LT1056 Test F...
Page 19 Application Note 48 IP VP RPLA DG1 DG2 DMG1 DMG2 DSUB D3A RS1 RS2 CXC2 VC CIN M1 PM1 M2 RSO PM2 RXC1 OUT VCL VCL RO2 VE VA 100k GCMVS GAVA GPLVP GNLVN GCLVI RD1 RD2 D4B ECLVCL CS D2 VN –– VN RNLA NOTE...
Page 20 Application Note 48 V+ DG1 DG2 GPL DMG1 DMG2 DSUB RPLA RPLB RS1 RS2 M1 M2 PM1 PM2 R2 RO2 GCM VE GCL VOD1 ECL RD1 RD2 CS VOD2 D4A RCL D2 +– GNL RNLA RNLB 0 NOTES: 1. SECTION SHOWN DOTTED OPTIONAL. 2. O...
Page 21 Application Note 48 1.0 In the circuits of Figure 10 the output current is sampled by a low value series resistor, RSO, typically 1Ω. The current proportional voltage drop across RSO is scaled by 0.5 ...
Page 22 Application Note 48 REFERENCES 1. Boyle, G.R., Cohn, B.M., Pederson, D.O., Solomon, from: Linear Technology Corporation, 1630 Mc Carthy J.E., “Macromodeling of Integrated Circuit Opera- Blvd, Milpitas...
Page 23 Application Note 48 (CM) signals by means of a common emitter (source) J2 and produces a current which adds/subtracts to/from capacitor, CE (CS, for JFET amps). However, using this the fixed current, ...
Page 24 Application Note 48 * ISS = (1.4e7)*(3e –11) = 420µA ISS 7 12 4.2000E-04 * comment out GOSIT with first column “*” * GOSIT 7 12 90 80 2.8000E-04 * INTERMEDIATE * Also, if a similar GBP is desired, adj...
Page 25 Application Note 48 Listing 1 * Linear Technology 8741 op amp model IP 7 4 1.9525E-03 * Written: 10-29-1990 12:55:37 Type: Bipolar NPN input, internal comp. DSUB 4 7 DM2 * Typical specs: * MODELS * Vo...
Page 26 Application Note 48 RPLA 7 70 1E4 RO2 7 99 25 RPLB 7 131 1E5 IP 3 4 328E-6 D4A 60 141 DM3 VB 9 0 DC 0 D4B 141 14 DM3 VC 3 53 DC 1.610 GNL 0 8 60 4 1 VE 54 4 DC .61 VE 6 14 3.0909 VLIM 7 8 DC 0 RNLA 60...
Page 27 Application Note 48 .MODEL QM2 PNP (IS=8.012E-16 BF=2.008E+02) .MODEL DM1 D (IS=3.718E-24) D3A 131 70 DM3 .MODEL DM2 D (IS=8.000E-16) D3B 13 131 DM3 .ENDS LT1078 GPL 0 8 70 7 1.0000E+00 VC 13 6 2.9595...
Page 28 Application Note 48 D2 20 21 DM1 VOD2 21 18 2.6932E+00 D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 1.4332E+00 RPLA 7 70 1.0000E+01 RPLB 7 131 1.0000E+03 D4A 60 141 DM3 D4B 141 14 DM3...

Manual Details

Brand Linear
Pages 28
File Size 289.85 KB
Published June 17, 2026
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Frequently Asked Questions

What is SPICE primarily useful for in circuit design?

SPICE is best suited for predictive analysis, feasibility checks, and worst-case limit testing, rather than being a perfect substitute for physical breadboarding.

How accurate are macromodels from IC vendors?

Macromodel quality depends on the information fed to it. The original source IC vendor remains the most reliable provider of model data.

What limitations should circuit designers be aware of when using SPICE models?

MACROMODELS always have inherent limitations because they are representations, and the ultimate performance depends on more than just the idealization level.

Can I trust a third-party supplier's op amp model for complex circuits?

Circuit designers must carefully evaluate if and how far they can trust any third-party macromodel to ensure accurate simulation results.