IDT IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM User Manual and Specifications
Summary
This high-speed asynchronous Dual-Port Static RAM is engineered for robust data storage requiring simultaneous read/write access from two independent ports. Designed with flexible Master/Slave modes and supporting both 3.3V and 2.5V logic levels, it integrates advanced features like internal port arbitration and semaphore signaling to ensure error-free operation. The accompanying documentation provides detailed electrical specifications, full pin configurations for various packages (TQFP, BGA), operational timing parameters, and industrial temperature guidelines, making it essential for system designers building complex, high-reliability embedded memory systems.
Page 1 Text Content
查询IDT70V631S供应商
HIGH-SPEED 3.3V 256K x 18
ASYNCHRONOUS DUAL-PORT IDT70V631S
STATIC RAM
Features True Dual-Port memory cells which allow simultaneous
access of the same memory location Fully asynchronous operation from either port High-speed access Separate byte controls for multiplexed bus and bus Commercial: 10/12/15ns (max.) matching compatibility Industrial: 12ns (max.) Supports JTAG features compliant to IEEE 1149.1 Dual chip enables allow for depth expansion without Due to limited pin count, JTAG is not supported on the external logic 128-pin TQFP package. IDT70V631 easily expands data bus width to 36 bits or LVTTL-compatible, single 3.3V (±150m V) power supply for more using the Master/Slave select when cascading more core than one device LVTTL-compatible, selectable 3.3V (±150m V)/2.5V (±100m V) M/S = VIH for BUSY output flag on Master, power supply for I/Os and control signals on each port M/S = VIL for BUSY input on Slave Available in a 128-pin Thin Quad Flatpack, 208-ball fine Busy and Interrupt Flags pitch Ball Grid Array, and 256-ball Ball Grid Array On-chip port arbitration logic Industrial temperature range (–40°C to +85°C) is available Full on-chip hardware support of semaphore signaling for selected speeds
between ports Functional Block Diagram UBL UBR LBL LBR
R/WL R/WR
CE0L CE0R CE1L CE1R
OEROEL
Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R
256K MEMORY ARRAY
I/O0L- I/O17L Din_L Din_R
A17L Address Address
ADDR_L ADDR_R
Decoder Decoder A0R
OEL ARBITRATION OER
INTERRUPT CE0R
SEMAPHORE
CE1L CE1R
LOGIC
R/WL R/WR
BUSYL BUSYR
SEML M/S SEMR
INTL INTR
JTAG TCK
NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2003
©2003 Integrated Device Technology, Inc. DSC-5622/5
Page Summary Contents For IDT IDT70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM User Manual and Specifications
Manual Details
| Brand | Dual |
|---|---|
| Pages | 23 |
| File Size | 304.66 KB |
| Published | June 06, 2026 |
Enter the captcha to get the download link:
Frequently Asked Questions
What temperature range does the device operate in?
It supports an industrial temperature range of –40°C to +85°C.
Can this DDR memory expand data bus width?
Yes, it can be easily expanded up to 36 bits or more using the Master/Slave select when cascading devices.
Which packaging options are available for this device?
It is available in a 128-pin Thin Quad Flatpack (TQFP), 208-ball fine Ball Grid Array (BGA), and 256-ball Ball Grid Array (BGA).
How does the device manage independent memory access?
The dual ports allow for separate, independent asynchronous access via on-chip port arbitration logic.