Fairchild DM74ALS09 Quad 2-Input AND Gate with Open Collector Outputs Data Manual

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74A 09 Q ad 2-In t A ate w ith en llecto r O tp ts

September 1986 Revised February 2000

DM74ALS09 Quad 2-Input AND Gate with Open Collector Outputs General Description Features This device contains four independent gates, each of which Switching specifications at 50 p F performs the logic AND function. The open-collector out-

Switching specifications guaranteed over full tempera-

puts require external pull-up resistors for proper logical

ture and VCC range

operation.

Advanced oxide-isolated, ion-implanted Schottky TTL

Pull-Up Resistor Equations

process Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart Improved AC performance over Schottky and low power Schottky counterparts

Where: N1 (IOH) = total maximum output HIGH current

for all outputs tied to pull-up resistor

N2 (IIH) = total maximum input HIGH current

for all inputs tied to pull-up resistor N3 (IIL) = total maximum input LOW current for all inputs tied to pull-up resistor

Ordering Code: Order Number Package Number Package Description DM74ALS09M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS09N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Y = AB

Inputs Output

H = HIGH Logic Level L = LOW Logic Level

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