AD2.5V to 5.5V, 400μA Quad Voltage Output, 8-10-12-Bit DACs in 16-Lead TSSOP AD5307 AD5317 AD5327 Data Sheet Manual User Guide

2.5 V to 5.5 V, 400 μA, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5307/AD5317/AD5327 FEATURES GENERAL DESCRIPTION AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP

The AD5307/AD5317/AD53271 are quad 8-,10-,12-bit buffered

A version: ±1 LSB INL; B version: ±0.625 LSB INL

voltage-output DACs in 16-lead TSSOP that operate from single

AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP

2.5 V to 5.5 V supplies and consume 400 μA at 3 V. Their on-

A version: ±4 LSB INL; B version: ±2.5 LSB INL

AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP chip output amplifiers allow the outputs to swing rail-to-rail with A version: ±16 LSB INL; B version: ±10 LSB INL a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize Low power operation: 400 μA @ 3 V, 500 μA @ 5 V versatile 3-wire serial interfaces that operate at clock rates up to

2.5 V to 5.5 V power supply 30 MHz; these parts are compatible with standard SPI, QSPI, Guaranteed monotonic by design over all codes MICROWIRE, and DSP interface standards. Power down to 90 n A @ 3 V, 300 n A @ 5 V (LDAC pin)

The references for the four DACs are derived from two reference

Double-buffered input logic

Buffered/unbuffered reference input options pins (one per DAC pair). These reference inputs can be configured Output range: 0 V to VREF or 0 V to 2 VREF as buffered or unbuffered inputs. Each part incorporates a power- Power-on reset to 0 V on reset circuit, ensuring that the DAC outputs power up to 0 V Simultaneous update of outputs (LDAC pin) and remain there until a valid write to the device takes place.

Asynchronous clear facility (CLR pin) There is also an asynchronous active low CLR pin that clears all Low power, SPI®-, QSPI™-, MICROWIRE™-, and DSP- DACs to 0 V. The outputs of all DACs can be updated simul- compatible 3-wire serial interface

taneously using the asynchronous LDAC input. Each part

SDO daisy-chaining option

contains a power-down feature that reduces the current

On-chip rail-to-rail output buffer amplifiers

consumption of the device to 300 n A @ 5 V (90 n A @ 3 V). The

Temperature range of −40°C to +105°C

parts can also be used in daisy-chaining applications using the

APPLICATIONS

SDO pin.

Portable battery-powered instruments

Digital gain and offset adjustment All three parts are offered in the same pinout, allowing users to

Programmable voltage and current sources select the amount of resolution appropriate for their application Programmable attenuators without redesigning their circuit board.

Industrial process control

FUNCTIONAL BLOCK DIAGRAM

VDD VREFAB

AD5307/AD5317/AD5327 GAIN-SELECT LOGIC

INPUT DAC STRING VOUTA

BUFFER

REGISTER REGISTER DAC A

INPUT DAC STRING

BUFFER VOUTB

REGISTER REGISTER DAC B

INTERFACE

SYNC LOGIC

INPUT DAC STRING VOUTC

BUFFER

REGISTER REGISTER DAC C

INPUT DAC STRING VOUTD

BUFFER

REGISTER REGISTER DAC D

POWER-ON

RESET POWER-DOWN LOGIC

CLRDCEN VREFCD PDLDAC GND

Figure 1.

1 Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

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