Texas Instruments UC1823A,B, UC1825A,B Data Sheet
Summary
Discover advanced PWM Controller ICs optimized for high-efficiency power conversion and robust system design. This comprehensive technical guide details enhanced functionality across modern switching regulator families, including improved error amplification, guaranteed current limits, and redesigned dual totem pole outputs capable of 2A peak currents. It is essential reading for electrical engineers and hardware designers building reliable DC/DC converters and offline power management circuits requiring precise voltage regulation and superior transient performance.
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application UC1823A,B/1825A,B INFO
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UC3823A,B/3825A,B
High Speed PWM Controller FEATURES DESCRIPTION Improved versions of the The UC3823A and the UC3825A family of PWM control ICs are UC3823/UC3825 PWMs improved versions of the standard UC3823 UC3825 family. Performance
enhancements have been made to several of the circuit blocks. Error ampli-
Compatible with Voltage or
fier gain bandwidth product is 12MHz while input offset voltage is 2m V. Cur-
Current-Mode Topologies
rent limit threshold is guaranteed to tolerance of 5%. Oscillator discharge
Practical Operation at Switching current is specified at 10m A for accurate dead time control. Frequency ac- Frequencies to 1MHz
curacy is improved to 6%. Startup supply current, typically 100µA, is ideal for off-line applications. The output drivers are redesigned to actively sink
50ns Propagation Delay to Output
current during UVLO at no expense to the startup current specification. In
High Current Dual Totem Pole
addition each output is capable of 2A peak currents during transitions.
Outputs (2A Peak)
Functional improvements have also been implemented in this family. The
Trimmed Oscillator Discharge Current UC3825 shutdown comparator is now high-speed overcurrent comparator
with threshold of 1.2V. The overcurrent comparator sets latch that en-
Low 100µA Startup Current
sures full discharge of the soft start capacitor before allowing restart.
Pulse-by-Pulse Current Limiting While the fault latch is set, the outputs are in the low state. In the event of Comparator
continuous faults, the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start
Latched Overcurrent Comparator With
period. The UC3825 Clock pin has become CLK/LEB. This pin combines
Full Cycle Restart
the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
(continued)
BLOCK DIAGRAM
UDG-95101* Note:
1823A,B Version Toggles Q and are always low
SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000
Page Summary Contents For Texas Instruments UC1823A,B, UC1825A,B Data Sheet
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 9 |
| File Size | 314.61 KB |
| Published | June 18, 2026 |
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Frequently Asked Questions
What is the primary function of the CLK/LEB pin on the UC3825?
It combines clock output and leading edge blanking adjustment functions, and it has been buffered for easier interfacing.
What peak current can the outputs (OUTA, OUTB) handle during transitions?
Each output is capable of 2A peak currents during transitions due to high current dual totem pole addition.
How does the UC3825 handle overcurrent faults before allowing a restart?
It sets a fault latch that keeps outputs low and ensures full discharge of the soft start capacitor before enabling a restart for accurate fault frequency control.
What is the required operating temperature range for different parts?
The electrical specifications vary by part, ranging from -55°C to +125°C (for UC1823A/B, etc.) to 0°C to +70°C (for UC3823A/B, etc.).