Texas Instruments SN54AHCT123A, SN74AHCT123A Data Sheet
Summary
This datasheet describes the SN74AHCT123A, a versatile edge-triggered dual retriggerable monostable multivibrator designed for precise timing and pulse generation in electronic logic circuits. It is intended for hardware designers and engineers requiring highly reliable pulse duration control. The manual provides comprehensive specifications, multiple packaging options (SOIC, TSSOP, etc.), and detailed technical guides on programming variable output pulse lengths using external resistors and capacitors.
Page 1 Text Content
查询5962-9861601Q2A供应商 SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420G – JUNE 1998 – REVISED APRIL 2003
Inputs Are TTL-Voltage Compatible SN54AHCT123A J OR W PACKAGE SN74AHCT123A D, DB, DGV, N, OR PW PACKAGE
Schmitt-Trigger Circuitry On A, B, and CLR
(TOP VIEW)
Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or 1A VCC
Active-Low Gated Logic Inputs 1B 1Rext/Cext 1CLR 1Cext
Retriggerable for Very Long Output Pulses
Overriding Clear Terminates Output Pulse
Latch-Up Performance Exceeds 100 m A Per
2Cext 2CLR
JESD 78, Class II
2Rext/Cext 2B
ESD Protection Exceeds JESD 22
GND 2A
– 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) SN54AHCT123A FK PACKAGE
(TOP VIEW)
description/ordering information These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is
1CLR 1Cext
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
NC NC
(CLR) input goes high.
The output pulse duration is programmed by
2Cext 2CLR
selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between 2R 1B
ex t/ ex
Rext/Cext and VCC. To obtain variable pulse 1A durations, connect an external variable resistance
between Rext/Cext and VCC. The output pulse NC – No internal connection 2A
duration also can be reduced by taking CLR low.
2B 1R ex t/ ex
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube SN74AHCT123AN SN74AHCT123AN
Tube SN74AHCT123AD
SOIC AHCT123A
Tape and reel SN74AHCT123ADR
40°C to 85°C
SSOP – DB Tape and reel SN74AHCT123ADBR HB123A TSSOP – PW Tape and reel SN74AHCT123APWR HB123A TVSOP – DGV Tape and reel SN74AHCT123ADGVR HB123A CDIP – J Tube SNJ54AHCT123AJ SNJ54AHCT123AJ
–55°C to 125°C CFP – W Tube SNJ54AHCT123AW SNJ54AHCT123AW
LCCC – FK Tube SNJ54AHCT123AFK SNJ54AHCT123AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments SN54AHCT123A, SN74AHCT123A Data Sheet
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 21 |
| File Size | 544.40 KB |
| Published | June 17, 2026 |
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Frequently Asked Questions
What packages are available for SN74AHCT123A?
It is offered in D, DB, DGV, N, and PW packages.
How do I program the output pulse duration?
Use external resistance and capacitance values connected to Cext and Rext/Cext pins.
What ESD protection does the device have?
It exceeds JESD 22: 2000V HBM, 200V MM, 1000V CDM.
How can I terminate the output pulse early?
Take the CLR input low to override and terminate the pulse.