Texas Instruments CDCU877, CDCU877A Data Sheet

查询CDCU877供应商

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

1.8-V Phase Lock Loop Clock Driver for External Feedback Pins (FBIN, FBIN) are Double Data Rate (DDR II ) Applications Used to Synchronize the Outputs to the

Input Clocks

Spread Spectrum Clock Compatible

Single-Ended Input and Single-Ended

Operating Frequency: 10 MHz to 400 MHz

Output Modes

Low Current Consumption: <135 m A

Meets or Exceeds JESD82-8 PLL Standard

Low Jitter (Cycle-Cycle): ±30 ps

for PC2-3200/4300

Low Output Skew: 35 ps

Fail-Safe Inputs

Low Period Jitter: ±20 ps Low Dynamic Phase Offset:: ±15 ps Low Static Phase Offset:: ±50 ps Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball µBGA (Micro Star Junior BGA, 0,65-mm pitch) and 40-Pin MLF

description The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C to 85°C.

AVAILABLE OPTIONS

TA 52-Ball BGA 40-Pin MLF

CDCU877ZQL

−40°C to 85°C CDCU877RTB

(Pb-Free) CDCU877AZQL

−40°C to 85°C CDCU877ARTB

(Pb-Free)

−40°C to 85°C CDCU877GQL −40°C to 85°C CDCU877AGQL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Micro Star Junior is a trademark of Texas Instruments.

Copyright  2004, Texas Instruments Incorporated
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