Texas Instruments CDC2582 Data Sheet
Summary
The CDC2582 is a high-performance, low-jitter clock driver designed to synthesize and distribute crystal-clear clock signals using a Phase-Lock Loop (PLL) architecture. Operating at 3.3V, it accepts differential LVPECL inputs to accurately manage output frequencies for synchronous DRAMs and advanced clock generation systems. This manual provides comprehensive details on the device's operation, including setting up nine configurable outputs via select lines, signal integrity features like internal resistors, and precise synchronization using a feedback input. Ideal for circuit designers needing high-speed, reliable, and stable clock distribution with minimal external components.
Page 1 Text Content
查询CDC2582供应商 CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
Low Output Skew for Clock-Distribution Application for Synchronous DRAMs and Clock-Generation Applications
Outputs Have Internal 26-Ω Series
Operates at 3.3-V VCC Resistors to Dampen Transmission-Line
Effects
Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs State-of-the-Art EPIC-ΙΙB Bi CMOS Design
Significantly Reduces Power Dissipation
Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double Distributed VCC and Ground Pins Reduce the Input Frequency Switching Noise No External RC Network Required Packaged in 52-Pin Quad Flatpack External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs
PAH PACKAGE
(TOP VIEW)
2Y IN
GND VCC
LK IN
3Y LK IN
VCC GND GND VCC 1Y2 4Y2
VCC GND LRC GND VCC 1Y3 4Y1 VCC GND GND GND GND VCC 2Y1 3Y3 VCC GND
description The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. Each output has an internal 26-Ω series resistor that improves the signal integrity at the load. The CDC2582 operates at 3.3-V VCC. The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN) signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized to the same frequency as the clock (CLKIN and CLKIN) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments CDC2582 Data Sheet
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 10 |
| File Size | 127.90 KB |
| Published | June 18, 2026 |
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Frequently Asked Questions
What voltage does the CDC2582 operate at?
The device operates at a 3.3-V V CC supply voltage.
How is clock synchronization achieved with this device?
The feedback input (FBIN) synchronizes the output clocks, and one output must be externally wired to FBIN for PLL operation.
Does the CDC2582 require external components like RC networks?
No, it does not require an external RC network because the loop filter for the PLL is included on chip.
What happens when I enable or disable outputs using OE?
Output-enable (OE) controls the outputs; high means low state, and low means active output.