Texas Instruments CDC2536 Data Sheet
Summary
The CDC2536 is a high-performance, low-jitter PLL clock driver designed for synchronizing and distributing clock signals in demanding digital applications. This manual provides detailed technical specifications for engineers implementing high-speed systems, including synchronous DRAM and microprocessors operating from 25 MHz to 100 MHz. It covers the architecture of the Phase-Lock Loop (PLL), out-of-the-box synchronization techniques, frequency division modes, and necessary system configurations, helping developers achieve precise, low-skew clock distribution without external RC networks.
Page 1 Text Content
查询CDC2536供应商 CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS SCAS377D – APRIL 1994 – REVISED OCTOBER 1998 Low Output Skew for Clock-Distribution DB PACKAGE (TOP VIEW)
and Clock-Generation Applications Operates at 3.3-V VCC
AVCC AVCC
Distributes One Clock Input to Six Outputs
AGND AGND
One Select Input Configures Three Outputs CLKIN FBIN to Operate at One-Half or Double the Input SEL TEST Frequency
OE CLR No External RC Network Required GND VCC
On-Chip Series Damping Resistors
VCC GND
External Feedback Pin (FBIN) Is Used to
GND VCC
Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM,
VCC GND
High-Speed Microprocessor
GND VCC
TTL-Compatible Inputs and Outputs 1Y3 2Y3
Outputs Drive 50-Ω Parallel-Terminated VCC GND
Transmission Lines State-of-the-Art EPIC-ΙΙB Bi CMOS Design Significantly Reduces Power Dissipation Distributed VCC and Ground Pins Reduce Switching Noise Packaged in Plastic 28-Pin Shrink Small-Outline Package
description The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50- transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external termination components. The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page Summary Contents For Texas Instruments CDC2536 Data Sheet
Manual Details
| Brand | Texas Instruments |
|---|---|
| Pages | 10 |
| File Size | 128.26 KB |
| Published | June 04, 2026 |
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Frequently Asked Questions
How must I complete the Phase-Lock Loop setup?
One device output must be externally wired to the FBIN pin for the PLL to function.
Does this clock driver require external termination resistors?
No, the CDC2536 includes on-chip series-damping resistors, eliminating the need for external RC networks.
What steps are needed after powering up or changing settings?
A stabilization time is required following power up and any changes to PLL reference, feedback signals, or SEL inputs.
Is this device suitable for critical applications like life support systems?
No. These semiconductor products are not designed or warranted for use in life-support devices or other critical applications.