SIEMENS SLx 24C64 Standard EEPROM ICs Data Sheet
Summary
Designed for reliable industrial applications, this low-power CMOS Serial EEPROM provides secure, non-volatile data storage up to 8K bits via a standard I²C two-wire bus interface. It features advanced capabilities like Page Protection Mode, making it ideal for embedded and control systems requiring high data integrity. The accompanying datasheet is an essential technical resource covering comprehensive electrical characteristics (AC/DC timing), operational guidelines, temperature ranges, and programming cycles. This manual serves hardware engineers and product designers selecting compact, reliable memory solutions for professional industrial and automotive equipment.
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查询SLE 24C64供应商
Standard EEPROM ICs SLx 24C64 64 Kbit (8192 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus
Data Sheet 1999-02-02
Page Summary Contents For SIEMENS SLx 24C64 Standard EEPROM ICs Data Sheet
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查询SLE 24C64供应商 Standard EEPROM ICs SLx 24C64 64 Kbit (8192 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Data Sheet 1999-02-02
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Edition 1999-02-02 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1999. All Rights Reserved. Attention please! As far as patents or o...
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SLx 24C64 Revision History: Current Version: 1999-02-02 Previous Version: 05.98, 07.98 Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Changes in the ...
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64 Kbit (8192 × 8 bit) Serial CMOS SLx 24C64 EEPROMs, I2C Synchronous 2-Wire Bus Preliminary Overview 1.1 Features Data EEPROM internally organized as 8192 bytes and 256 pages × 32 bytes Page Protecti...
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SLx 24C64 Ordering Information Type Ordering Code Package Temperature Voltage SLA 24C64-D Q67100-H3768 P-DIP-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C64-D/P Q67100-H3762 SLA 24C64-S Q67100-H3767 P-D...
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SLx 24C64 Pin Definitions and Functions Table 1 Pin No. Symbol Function 1, 2, 3 CS0, CS1, CS2 Chip select inputs VSS Ground SDA Serial bidirectional data bus SCL Serial clock input WP Write protection...
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SLx 24C64 Description The SLx 24C64 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 8192 × 8 bit. The data memory is divided into pages. The 32 bytes ...
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SLx 24C64 CCV CS0 CS1 CS2SSV Programming Chip Address Control Control Logic H.V. Pump Start/ Stop Logic Serial SCL Control Logic Address EEPROM Logic DEC Page Logic Y DEC Dout/ACK IEB02525 Figure 2 Bl...
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SLx 24C64 I2C-Bus Characteristics Access to the SLx 24C64 device is given via the I2C bus. This bidirectional bus consists of two wires SCL and SDA for clock and data. The protocol is master/slave ori...
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SLx 24C64 The conventions for the serial clock line and the bidirectional data line are shown in figure 4. SDA ACK ACK START Condition Data allowed Acknowledge STOP Condition to Change IED02128 Figure...
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SLx 24C64 Device Addressing and EEPROM Addressing After a START condition, the master always transmits a command byte CSW or CSR. After the acknowledge of the EEPROM control bytes follow, their conten...
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SLx 24C64 Command Byte (CSW) Data Transfer to EEPROM SDA CS2 CS1 CS0 A12 A10 A9 A8A11 ACKACK START from Master Acknowledge from EEPROMAcknowledge from EEPROM SDA A6 A5 A0A1A2A3A4A7 ACK Acknowledge fro...
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SLx 24C64 Write Operations Changing of the EEPROM data is initiated by the master with the command byte CSW. Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one programming ...
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SLx 24C64 5.2 Page Write Address Setting The page write procedure is the same as the byte write procedure up to the first data byte. In a page write instruction however, entry of the EEPROM address by...
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SLx 24C64 The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter 5.3, A...
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SLx 24C64 STOP from Master initiates erase/write cycle START from Master CSR CSR CSR SSDA 1P Acknowledge of EEPROM indicates complete erase/ write cycle STOP from Master initiates erase/write cycle ST...
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SLx 24C64 Read Operations Reading of the EEPROM data is initiated by the Master with the command byte CSR. 6.1 Random Read Random read operations allow the master to access any memory location. Addres...
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SLx 24C64 6.2 Current Address Read The EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read ...
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SLx 24C64 6.3 Sequential Read A sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM ...
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SLx 24C64 Page Protection Mode TM The page protection mode is supported by the SLx 24C64.../P types only. For example SLA 24C64-D/P has the same functionality as SLA 24C64-D enhanced by page protectio...
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SLx 24C64 7.1 Protection Bit Handling The bits of the protection memory can be addressed directly for reading or programming. A protection bit address corresponds to the lowest address within the resp...
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SLx 24C64 7.2 Protection Bit Write and Erase For writing or erasing a protection bit the data of the respective page have to be known by the master. The master has to present the page data as a refere...
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SLx 24C64 bytes have to be identical to the bytes stored in ascending address order within the same page. A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to l...
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SLx 24C64 Electrical Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production...
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SLx 24C64 8.2 DC Characteristics (cont’d) Parameter Symbol Limit Values Units Test Condition min. typ. max. Input high VIH 0.7 VCC VCC 0.5 voltage Output low VOL 0.4 IOL 3 m A; VCC 5 V voltage IOL 2.1...
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SLx 24C64 8.3 AC Characteristics Parameter Symbol Limit Values Limit Values Units VCC = 2.7-5.5 V VCC = 4.5-5.5 V min. max. min. max. SCL clock frequency f SCL k Hz Clock pulse width low tlow 4.7 1.2 ...
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SLx 24C64 LOWt HIGH SU.STAt SU.DAT HD.STAt HD.DATt SU.STO BUFt SDA In Start Condition Stop Condition AA DHtt SDA Out IED02127 Figure 18 Bus Timing Data Semiconductor Group 1999-02-02
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SLx 24C64 Package Outlines P-DIP-8-3 (Plastic Dual In-line Package) P-DSO-8-2 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Boo...
Manual Details
| Brand | Siemens |
|---|---|
| Pages | 28 |
| File Size | 279.33 KB |
| Published | June 01, 2026 |
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Frequently Asked Questions
What type of bus interface does this EEPROM utilize?
It uses a two-wire serial interface bus and is compatible with IC-Bus standards.
Does this chip offer protection against unintended data changes?
Yes, Page Protection Mode is available for SLx 24C64.../P types to protect the EEPROM.
What extended temperature ranges are supported by the component?
The device is available in Industrial (-40°C to +85°C) and Automotive (-40°C to +125°C) grades.
Can this component be used in life-support systems?
Yes, but components for life-support devices require express written approval from the Semiconductor Group of Siemens AG.