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现货库存、技术资料、百科信息、热点资讯,精彩尽在鼎好! K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Document Title 64M x 8 Bits NAND Flash Memory Revision History Revision No. History Draft Date Remark 0.0 Initial issue. Nov. 10th 2005 Advance 0.1 2.7V p...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY 64M x 8 Bits NAND Flash Memory PRODUCT LIST Part Number Vcc Range Organization PKG Type K9F1208R0C-J 1.65V ~ 1.95V FBGA K9F1208B0C-P 2.5V ~ 2.9V TSOP1 K9F...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN CONFIGURATION (TSOP1) 0. 0. 8+0 -0 .0 0. -0 .0 TY K9F1208X0C-PCB0/PIB0 N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O7 N.C I/O6 R/B I/O5 RE I/O4 CE N.C N.C N...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN CONFIGURATION (FBGA) K9F1208X0C-JCB0/JIB0 R/B/WE/CEVss ALE/WP NC /RE CLE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NCNC NC I/O0 NC NC Vcc ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY 63-Ball FBGA (measured in millimeters) Top View Bottom View #A1 INDEX MARK(OPTIONAL) (Datum A) (Datum B) Side View 0.10MAX
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PIN DESCRIPTION Pin Name Pin Function DATA INPUTS/OUTPUTS I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM VCC VSS X-Buffers Latches 512M + 16M Bits & Decoders NAND Flash ARRAY Y-Buffers Latches & Decoders (...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Product Introduction The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col- umns are lo...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit 1.8V Device 2.7V/3.3V Device VCC -0.6 to + 2.45 -0.6 to + 4.6 Voltage on any pin relative to VSS -0....
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY VALID BLOCK Parameter Symbol Min Typ. Max Unit Valid Block Number NVB 4,026 4,096 Blocks NOTE : 1. The K9F1208X0C may include invalid blocks when first sh...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Program / Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time t PROG(1) µs Number of Partial Program Cycles Main Array cycle in the Same ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY AC CHARACTERISTICS FOR OPERATION Parameter Symbol Min Max Unit Data Transfer from Cell to Register t R µs ALE to RE Delay t AR ns CLE to RE Delay t CLR ns...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose relia...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash me...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Read D...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Pointer Operation of K9F1208X0C Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY * Command Latch Cycle t CLS t CLH t CS t CH t ALS t ALH t DS t DH I/OX Command * Address Latch Cycle t CLS t WC t WC t WC t WP t WP t WP t WP t WH t WH t ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY * Input Data Latch Cycle t CLH t ALS t WP t WP t WP≈ t DH t DH t DH t DS t DS t DS DIN 0 DIN 1 DIN n * Serial access Cycle after Read(CLE=L, WE=H, ALE=L) ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Status Read Cycle (During Ready State) t CLR t CLS t CLH t CH t WP t CEA t CHZ t OHt WHR RE t RP t DH t REAt IR t RHZ I/OX 70h/7Ah Status Output Status Re...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READ1 OPERATION (READ ONE PAGE) 1) On K9F1208X0C-P t CEH CE must be held CE low during t R t CHZ t CRY t RHZ t R t RC N Address 00h or 01h A0 ~ A7 A9 ~ A1...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Read2 Operation (Read One Page) On K9F1208X0C-P CE must be held low during t R Dout n+m I/OX 50h A0 ~ A7 A9 ~ A16 A17 ~ A24 Selected Row M Address A0~A3 :...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Page Program Operation t WC t WC t WC t PROGt WB Din Din I/OX 80h A17 ~ A24A9 ~ A16 A25 10h527A0 ~ A7 70h I/O0 Sequential Data Column 1 up to 528 Byte Dat...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Read ID Operation t REA 90h 00h ECh 76h 5Ah 3Fh Read ID Command Address. 1cycle Maker Code Device Code ID Defintition Table 90 ID : Access command = 90H V...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 7. Read1 Operation On K9F1208X0C-P CE CE must be held low during t R Start Add.(4Cycle)00h Data Output(Sequential) (00h Command) (01h Command) 1) M...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 8. Read2 Operation On K9F1208X0C-P CE CE must be held low during t R 50h Start Add.(4Cycle)I/OX Data Output(Sequential) Spare Field (A4 ~ A7 : Fixe...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 9. Sequential Row Read1 Operation (only for K9F1208X0C-P valid within a block) I/OX 00h Start Add.(4Cycle) Data Output Data Output Data Output 1st ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 5...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY BLOCK PROTECT Each block is protected from programming and erasing, controlled by the protect flag written in a specified area in the block. Block Proctec...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Figure 14. Read Block Status I/OX 00h A9 ~ A16A0 ~ A7 A17 ~ A24 A25 7Ah Status A0~7 : 00h, A9~13 : 0 fixed, A14~25 : 0 to 4095 Table 3. Status Register De...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program o...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or ...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. T...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY @ Vcc = 1.8V, Ta = 25°C , CL = 30p F Ibusy 0.85 tr 100n tr, tf [s 1m30 tr, tf [s tr, tf [s 1.7 1.7 1.7 tf Rp(ohm) @ Vcc = 2.7V, Ta = 25°C , CL = 30p F 2.3...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An interna...
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K9F1208U0C K9F1208R0C K9F1208B0C FLASH MEMORY WP AC Timing guide Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Figure A...