Motorola MC74AC112 MC74ACT112 Data Handbook

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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH

Outputs Source/Sink 24 m A N SUFFIX ′ACT112 Has TTL Compatible Inputs CASE 648-08 PLASTIC

CONNECTION DIAGRAM VCC CD1 CD2 CP2 K2 J2 SD2 Q2

D SUFFIX

CD SD CASE 751B-05

PLASTIC

CP CP

LOGIC SYMBOL

CP1 K1 J1 SD1 Q1 Q1 Q2 GND

MODE SELECT — TRUTH TABLE SD SD

QJ QJ

Inputs Outputs

Operating Mode

SD CD

CP CP

Set Reset (Clear)

CD CD

*Undetermined Toggle Load “0” (Reset)

VCC = PIN 16

Load “1” (Set)

GND = PIN 8

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, l = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input

(or output) one set-up time prior to the HIGH to LOW clock transition.

FACT DATA 5-1