Motorola MC10E156 MC100E156 Data Handbook & Manuals

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

3-BIT 4:1

950ps Max. D to Output

MUX-LATCH

850ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

VCCOD2a D2b D2c D2d D1a D1b

FN SUFFIX

SEL0 Q2

PLASTIC PACKAGE CASE 776-02

SEL1 Q2

MR VCC

VEE Q1 LOGIC DIAGRAM

LEN1 Q1

LEN2 VCCO MUX

D1d D0a D0b D0c D0d VCCO Q0 D1b 4:1

* All VCC and VCCO pins are tied together on the die. Q1

PIN NAMES

Pin Function D2a

D0x D3x Input Data

SEL0, SEL1 Select Inputs D2c

EN Q2

LEN1, LEN2 Latch Enables D2d MR Master Reset Q0 Q2 True Outputs Q0 Q2 Inverted Outputs SEL0

FUNCTION TABLE

SEL1 SEL0 Data

2–1 REV 3 Motorola, Inc. 1996