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Fairchild Semiconductor FAN5026 Dual DDR Dual-Output PWM Controller Data Sheet

Summary

This high-performance PWM controller provides an integrated dual solution for powering DDR memory in demanding applications. It features reliable and highly efficient regulation of two system voltages using advanced modes like DDR and out-of-phase operation, ensuring stable power for complex components. The comprehensive manual guides engineers through implementation details, covering signal definitions, wiring diagrams, functional specifications, protective measures (OV/UV protection), and voltage tracking schemes. This IC is ideal for designers building high-performance desktop computers, graphics cards, and servers that require a robust, energy-efficient core memory power solution.

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FA 5026 D al D /D al-O tp t P tro ller

October 2005

FAN5026 Dual DDR/Dual-Output PWM Controller Features General Description Highly flexible dual synchronous switching PWM The FAN5026 PWM controller provides high efficiency controller includes modes for: and regulation for two output voltages adjustable in the

DDR mode with in-phase operation for reduced range from 0.9V to 5.5V that are required to power I/O, channel interference chip-sets, and memory banks in high-performance com- puters, set top boxes, and VGA cards. Synchronous rec-

90° phase shifted two-stage DDR Mode for reduced

tification contributes to high efficiency over a wide range

input ripple

of loads. Efficiency is even further enhanced by using

Dual Independent regulators 180° phase shifted

MOSFET’s R as a current sense component.

DS(ON)

Complete DDR Memory power solution

Feed-forward ramp modulation, average current mode

VTT Tracks VDDQ/2

control scheme, and internal feedback compensation

VDDQ/2 Buffered Reference Output

provide fast response to load transients. Out-of-phase

Lossless current sensing on low-side MOSFET or operation with 180° phase shift reduces input current Precision current sensing using sense resistor ripple. The controller can be transformed into a com-

VCC Under-voltage Lockout plete DDR memory power supply solution by activating a Wide power input range: 3 to 16V designated pin. In DDR mode of operation one of the channels tracks the output voltage of another channel

Excellent dynamic response with Voltage

and provides output current sink and source capability —

Feed-Forward and Average Current Mode control

features essential for proper powering of DDR chips. The

Power-Good Signal

buffered reference voltage required by this type of mem-

Supports DDR-II and HSTL

ory is also provided. The FAN5026 monitors these out-

TSSOP28 package puts and generates separate PGx (power good) signals

when the soft-start is completed and the output is within

Applications ±10% of its set point. A built-in over-voltage protection

prevents the output voltage from going above 120% of

DDR V and V voltage generation DDQ TT

the set point. Normal operation is automatically restored

Desktop computer

when the over-voltage conditions go away. Under-volt-

Graphics cards

age protection latches the chip off when either output drops below 75% of its set value after the soft-start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external cur- rent-sense resistor may optionally be used.

Ordering Information

Part Number Temperature Range Package Packing FAN5026MTC -40°C to 85°C TSSOP-28 Rails FAN5026MTCX -40°C to 85°C TSSOP-28 Tape and Reel

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 Rev. 1.0.5

Page Summary Contents For Fairchild Semiconductor FAN5026 Dual DDR Dual-Output PWM Controller Data Sheet

Page 1 FA 5026 D al D /D al-O tp t P tro ller October 2005 FAN5026 Dual DDR/Dual-Output PWM Controller Features General Description Highly flexible dual synchronous switching PWM The FAN5026 PWM controller p...
Page 2 FA 5026 D al D /D al-O tp t P tro ller Block Diagrams VCC VIN (BATTERY) +5 FAN5026 = 3 to 16V ILIM1 VOUT1 L OUT1 PWM 1 COUT1 DDR VIN (BATTERY) ILIM2/ VOUT2 REF2 = 1.8VL OUT2 PWM 2 COUT2 Figure 1. Dual...
Page 3 FA 5026 D al D /D al-O tp t P tro ller Pin Configurations AGND VCC LDRV1 LDRV2 PGND1 PGND2 SW1 SW2 HDRV1 HDRV2 BOOT1 BOOT2 ISNS1 ISNS2 FAN5026 EN1 EN2 GND GND VSEN1 VSEN2 ILIM1 ILIM2/REF2 SS1 SS2 DDR ...
Page 4 FA 5026 D al D /D al-O tp t P tro ller Pin Definitions (Continued) Pin Number Pin Name Pin Function Description DDR DDR Mode Control . High = DDR mode. Low = 2 separate regulators operating 180° out o...
Page 5 FA 5026 D al D /D al-O tp t P tro ller Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current LDRV, HD...
Page 6 FA 5026 D al D /D al-O tp t P tro ller CBOOT BOOTVDD POR/UVLO DDR HDRV OVP SW ADAPTIVE Q2 L OUT GATE VDD CONTROL LOGIC DDR LDRV VIN CLK RSENSEILIM det. ISNS CURRENT PROCESSING EAVSEN PGOOD Reference a...
Page 7 FA 5026 D al D /D al-O tp t P tro ller Typical Applications VIN = 3 to 16V VCC+5 BOOT1 Q1A C5 HDRV1 R3 ILIM1 L1 VDDQ = 2.5V EN1 C6 PWM 1 Q1B SS1 LDRV1 PGND2 R5 ISNS1 VSEN1 DDR R1 BOOT2 EN2 D2 17C3 HDR...
Page 8 FA 5026 D al D /D al-O tp t P tro ller Typical Applications (Continued) VIN = 3 to 16V VCC+5 BOOT1 Q1A C5 HDRV1 R2 ILIM1 L1 2.5V@4A EN1 C6 PWM 1 SS1 LDRV1 R4 12C2 +5 PGND2 R3 ISNS1 PG1 VSEN1 EN2 BOOT2...
Page 9 FA 5026 D al D /D al-O tp t P tro ller Circuit Description Overview The FAN5026 is a multi-mode, dual channel PWM con- VDDQ troller intended for graphic chipset, SDRAM, DDR DRAM or other low output vo...
Page 10 FA 5026 D al D /D al-O tp t P tro ller Current Processing Section The following discussion refers to Figure 10. VDDQ The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on...
Page 11 FA 5026 D al D /D al-O tp t P tro ller Setting the Current Limit Gate Driver Section A ratio of ISNS is also compared to the current The adaptive gate control logic translates the internal established...
Page 12 FA 5026 D al D /D al-O tp t P tro ller The optimal value of C(Z) is: OUT( OUT( )× Protection REF EA Out The converter output is monitored and protected against extreme overload, short circuit, over-vo...
Page 13 FA 5026 D al D /D al-O tp t P tro ller Similarly, if an output short-circuit or severe load tran- where ∆I is the inductor ripple current and ∆VOUT is the sient causes the output to droop to less than...
Page 14 FA 5026 D al D /D al-O tp t P tro ller As an example, if average IVDDQ is 3A, and average IVTT fore is also representative of gate charge (QG). CISS = is 1A, IVDDQ current will be about 3.5A. If avera...
Page 15 FA 5026 D al D /D al-O tp t P tro ller θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). Layout Cons...
Page 16 FA 5026 D al D /D al-O tp t P tro ller Mechanical Dimensions 28-Pin TSSOP 0.51 TYP 0.2 0.65 0.42B ALL Lead Tips PIN # 1 IDENT LAND PATTERN RECOMMENDATION – A 1.2 MAX 4. 0. +0.15 0.90 See Detail A ALL ...
Page 17 FA 5026 D al D /D al-O tp t P tro ller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive ...

Manual Details

Brand Fairchild
Pages 17
File Size 174.03 KB
Published June 16, 2026
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Frequently Asked Questions

What voltage range can the two outputs be regulated at?

Each output voltage is adjustable within a range from 0.9V to 5.5V.

How does the controller protect against extreme voltage conditions?

It includes over-voltage protection (above 120%) and under-voltage protection, which latches the chip off if the output drops below 75% of its set value.

What efficiency modes are available for optimal operation?

Operating options include in-phase mode, 90° phase shifted two-stage DDR Mode, or 180° phase shifted MOSFETs for enhanced efficiency.