Fairchild FDG6321C Dual N & P Channel Digital FET Data Manual
Summary
This datasheet details the FDG6321C, a dual N & P Channel Digital FET engineered with advanced DMOS technology. Designed for optimal performance in low-voltage circuits (e.g., 3V systems), this solid-state switch is an efficient replacement for traditional bipolar digital transistors while offering superior reliability and an ultra-compact SC70-6 footprint. The manual provides comprehensive information on absolute maximum ratings, dynamic characteristics, thermal behavior, and electrical parameters, making it an essential resource for electronic engineers implementing high-density, low-power switching solutions.
Page 1 Text Content
November 1998
FDG6321C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 Ω @ VGS= 4.5V. effect transistors are produced using Fairchild's proprietary,
RDS(ON) = 0.60 Ω @ VGS= 2.7 V.
high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 Ω @ VGS= -4.5V. This device has been designed especially for low voltage
RDS(ON) = 1.5 Ω @ VGS= -2.7V.
applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, Very small package outline SC70-6. this dual digital FET can replace several different digital
Very low level gate drive requirements allowing direct
transistors, with different bias resistor values.
operation in 3 V circuits(VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness (>6k V Human Body Model).
SC70-6 Super SOTTM-6 SOIC-14SO-8SOT-8SOT-23
SC70-6
Absolute Maximum Ratings TA = 25o C unless otherwise noted Symbol Parameter N-Channel P-Channel Units
VDSS Drain-Source Voltage -25
VGSS Gate-Source Voltage 8 -8
ID Drain Current - Continuous 0.5 -0.41
- Pulsed 1.5 -1.2
PD Maximum Power Dissipation (Note 1) 0.3
TJ,TSTG Operating and Storage Temperature Ranger -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D k V
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W
© 1998 Fairchild Semiconductor Corporation FDG6321C Rev. D
Page Summary Contents For Fairchild FDG6321C Dual N & P Channel Digital FET Data Manual
Manual Details
| Brand | Fairchild |
|---|---|
| Pages | 9 |
| File Size | 72.80 KB |
| Published | May 30, 2026 |
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Frequently Asked Questions
What circuits is this dual FET designed to replace?
It can act as a replacement for bipolar digital transistors, enabling operation in low voltage 3 V circuits.
What is the required thermal resistance calculation ($R_{JA}$)?
The junction-to-ambient thermal resistance ($R_{ heta JA}$) must be determined by the user's specific board design to guarantee accurate power dissipation analysis.
Can this component be used in life support devices?
No. Fairchild’s products are not authorized for use as critical components in life support systems without express written approval.
What is the maximum operating temperature range?
The device operates and handles storage temperatures ranging from -55°C to 150°C.