Fairchild FDG6304P Dual P-Channel, Digital FET Data Manual

July 1999

FDG6304P Dual P-Channel, Digital FET

General Description Features

-25 V, -0.41 A continuous, -1.5 A peak.

These dual P-Channel logic level enhancement mode

field effect transistors are produced using Fairchild's RDS(ON) = 1.1 Ω @ VGS= -4.5 V,

proprietary, high cell density, DMOS technology. This RDS(ON) = 1.5 Ω @ VGS= -2.7 V. very high density process is especially tailored to

Very low level gate drive requirements allowing direct

minimize on-state resistance. This device has been

operation in 3 V circuits (VGS(th) < 1.5 V).

designed especially for low voltage applications as a replacement for bipolar digital transistors and small

Gate-Source Zener for ESD ruggedness

signal MOSFETs.

(>6k V Human Body Model). Compact industry standard SC70-6 surface mount package.

SOT-23 Super SOTTM-6 Super SOTTM-8 SO-8

SOT-223SC70-6

G2 1 or 4 *

6 or 3

2 or 5 5 or 2

SC70-6 4 or 1 *

3 or 6

*The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device.

Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter FDG6304P Units VDSS Drain-Source Voltage -25 VGSS Gate-Source Voltage -8 ID Drain/Output Current - Continuous -0.41

- Pulsed -1.5

PD Maximum Power Dissipation (Note 1) 0.3 TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C ESD Electrostatic Discharge Rating MIL-STD-883D 6.0 k V

Human Body Model (100 p F / 1500 Ω)

THERMAL CHARACTERISTICS

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) °C/W

FDG6304P Rev.E1