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Fairchild FAN5026 Product Specifications

Summary

This high-efficiency Dual DDR/Dual-Output PWM Controller is a robust power management solution designed for sophisticated applications including servers, desktop PCs, and set-top boxes. The device features advanced synchronous switching circuitry and low-loss current sensing, ensuring reliable voltage regulation and optimal performance across memory banks (DDR). This manual provides technical specifications covering operational modes, system integration details, pin definitions, thermal optimization, and comprehensive protection schemes (OVP/UVLO), making it essential for electrical engineers and product designers building reliable, high-power computing systems.

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l D / D l-O tp t P tro lle

March 2011

FAN5026 Dual DDR / Dual-Output PWM Controller Features Description

Highly Flexible, Dual Synchronous Switching PWM The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable in the

Controller that Includes Modes for:

range of 0.9V to 5.5V required to power I/O, chip-sets,

- DDR Mode with In-phase Operation for

and memory banks in high-performance computers,

Reduced Channel Interference

set-top boxes, and VGA cards. Synchronous - 90° Phase-shifted, Two-stage DDR Mode rectification and hysteretic operation at light loads for Reduced Input Ripple contribute to high efficiency over a wide range of loads. Efficiency is enhanced by using MOSFET RDS(ON) as a

- Dual Independent Regulators, 180° Phase

current-sense component.

Shifted

Complete DDR Memory Power Solution

Feedforward ramp modulation, average-current mode - VTT Tracks VDDQ/2 control, and internal feedback compensation provide fast response to load transients. Out-of-phase operation

- VDDQ/2 Buffered Reference Output

with 180-degree phase shift reduces input current

Lossless Current Sensing on Low-Side MOSFET or ripple. The controller can be transformed into a Precision Over-Current Using Sense Resistor complete DDR memory power supply solution by

activating a designated pin. In DDR Mode, one of the

VCC Under-Voltage Lockout

channels tracks the output voltage of another channel Wide Input Range: 3V to 16V and provides output current sink and source capability — essential for proper powering of DDR chips. The

Excellent Dynamic Response with Voltage

buffered reference voltage required by this type of

Feedforward and Average Current-Mode Control

memory is also provided. The FAN5026 monitors these Power-Good Signal outputs and generates separate PGx (power good) signals when the soft-start is completed and the output

Supports DDR-II and HSTL

is within ±10% of the set point.

28-Lead Thin-Shrink Small-Outline Package

Over-voltage protection prevents the output voltage from exceeding 120% of the set point. Normal operation

Applications

is automatically restored when over-voltage conditions cease. Under-voltage protection latches the chip off

DDR VDDQ and VTT Voltage Generation

when output drops below 75% of the set value after the

PC Dual Power Supply soft-start sequence for this output is completed. An

adjustable over-current function monitors the output

Server DDR Power

current by sensing the voltage drop across the lower Desktop Computer MOSFET. If precision current-sensing is required, an external current-sense resistor may be used.

Graphics Cards

Related Resources Application Note — AN-6002 Component Calculations and Simulation Tools

Ordering Information

Operating

Part Number Temperature Package Packing Method

Range

FAN5026MTCX -40 to +85°C 28-Lead Thin-Shrink Small-Outline Package (TSSOP) Tape and Reel

© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8

Page Summary Contents For Fairchild FAN5026 Product Specifications

Page 1 l D / D l-O tp t P tro lle March 2011 FAN5026 Dual DDR / Dual-Output PWM Controller Features Description Highly Flexible, Dual Synchronous Switching PWM The FAN5026 PWM controller provides high effici...
Page 2 l D / D l-O tp t P tro lle Block Diagrams Figure 1. Dual-Output Regulator Figure 2. Typical Application © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 2
Page 3 l D / D l-O tp t P tro lle Pin Configuration Figure 3. TSSOP-28 Pin Definitions Pin # Name Description Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured 1 ...
Page 4 l D / D l-O tp t P tro lle Pin Definitions Pin # Name Description 11 ILIM1 Current Limit 1. A resistor from this pin to GND sets the current limit. 12 SS1 Soft Start. A capacitor from this pin to GND ...
Page 5 l D / D l-O tp t P tro lle Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating co...
Page 6 l D / D l-O tp t P tro lle Electrical Characteristics Recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Power Supplies LDRV, HDRV Open, VSEN Fo...
Page 7 l D / D l-O tp t P tro lle Typical Application Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM Description Qty. Ref. Vendor Part Number Capacitor 68µf, Tantalum, 25V, ESR 150mΩ 1 C1 AVX...
Page 8 l D / D l-O tp t P tro lle Typical Applications (Continued) Figure 6. Dual Regulator Application Table 2. Dual Regulator BOM Description Qty. Ref. Vendor Part Number Capacitor 68µf, Tantalum, 25V, ESR...
Page 9 l D / D l-O tp t P tro lle Circuit Description Overview CLK The FAN5026 is a multi-mode, dual-channel PWM controller intended for graphic chipset, SDRAM, DDR VD DQ DRAM, or other low-voltage power app...
Page 10 l D / D l-O tp t P tro lle Since Initialization and Soft Start Assuming EN is HIGH, FAN5026 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an inte...
Page 11 l D / D l-O tp t P tro lle Duty Cycle Clamp voltage excursion is detected, limiting the maximum duty cycle to: During severe load increase, the error amplifier output can go to its upper limit, pushin...
Page 12 l D / D l-O tp t P tro lle For this type of modulator, a Type-2 compensation If a larger inductor value or low-ESR values are circuit is usually sufficient. To reduce the number of required by the app...
Page 13 l D / D l-O tp t P tro lle Over-Voltage / Under-Voltage Protection Similarly, if an output short-circuit or severe load Should the VSNS voltage exceed 120% of VREF (0.9V) transient causes the output t...
Page 14 l D / D l-O tp t P tro lle (QG). CISS = CGD + CGS and it controls t1, t2, and t4 Two-Stage Converter Case timing. CGD receives the current from the gate driver In DDR Mode (Figure 5), the VTT power in...
Page 15 l D / D l-O tp t P tro lle )SW(G )SW(G Layout Considerations VV (28) DRIVER SPCC Switching converters, even during normal operation, produce short pulses of current that could cause RR GATEDRIVER subs...
Page 16 l D / D l-O tp t P tro lle Physical Dimensions Figure 18. 28-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers consideri...
Page 17 l D / D l-O tp t P tro lle © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 17

Manual Details

Brand Fairchild
Pages 17
File Size 752.23 KB
Published June 01, 2026
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Frequently Asked Questions

What input voltage range does the FAN5026 controller support?

The unit supports a wide input range spanning from 3V to 16V.

How does the device handle over-voltage or under-voltage conditions?

It features both over-voltage protection (which restores automatically) and under-voltage protection (which latches the chip off if voltage drops below 75% of the set value).

What is the purpose of DDR Mode operation?

DDR Mode provides high efficiency through advanced techniques like In-phase Operation, 90° Phase-shifted, and Two-stage regulation for memory power solutions.

How can users monitor output current precisely?

For precision current-sensing, an external current-sense resistor may be used to optimize monitoring.