Vishay AN805 Data Handbook / Manual

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AN805

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Vishay Siliconix

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PWM Optimized Power MOSFETs for Low-Voltage DC/DC Conversion

Designers of low-voltage dc-to-dc converters have two main [ ] The value of the parameter before the parenthesis is dependent concerns: reducing size and reducing losses. As a way of reducing on the parameter within the parenthesis. size, designers are increasing switching frequencies. But the result has been reduced converter efficiency. To minimize losses, Drain MOSFET manufacturers have generally focused on lowering

on-resistance. But the results have not been optimal for dc-to-dc conversion designs, since gate charge and switching speed issues have been largely ignored. The dominant losses associated with

MOSFETs were once conduction losses, but this is no longer the

case.

Vishay Siliconix’s new family of PWM optimized MOSFETs has r DS(on)

been designed to give the highest efficiency available for a given

on-resistance in switching applications such as dc-to-dc conversion. These new devices provide a very low gate charge per unit of on-resistance, in addition to fast switching times. The Source

result is reduced gate drive and crossover losses, allowing on du ct io at ha rg

designers of dc-to-dc converters to simultaneously reduce the FIGURE 1. Generic MOSFET model with body diode omitted.

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design footprint and increase efficiency.

MOSFET Losses where:

A simplistic model of power loss in a MOSFET used in a dc-to-dc I2RMS The RMS current in the MOSFET (A)

converter (Figure 1) can be calculated if we know the RMS, the r DS(on) On-resistance of the device for a given drive voltage current through the MOSFET, the duty cycle, the gate voltage, and and junction temperature. the r DS(on) of the MOSFET. This model can then be used to

VGS The peak driver gate voltage for the MOSFET (V)

compare the efficiency of designs using Vishay Siliconix’s new

[TJ] Junction temperature of the MOSFET

PWM optimized MOSFETs versus conventional and low-threshold power MOSFETs. Duty factor of the MOSFET (Ratio of on time to off

time)

The equation that defines the losses associated only with Qg Total gate charge for the MOSFET at a given gate

on-resistance and the gate drive is: voltage (C) Frequency of MOSFET switching (Hz)

I2RMS r DS(on)VGS

Using Equation 1 we can obtain a plot of power loss (gate loss + r DS(on) loss) as a function of gate voltage at varying switching

VGS (Watts) Eq1

gVGS frequencies (Figure 2). [1]

Si6801 Power Loss, QG, r DS VGS Technology Comparison: 1 MHz Power Loss

VGS VGS

FIGURE 2. Power loss for PWM optimized Si6801 p-channel FIGURE 3. Gate losses and on-resistance losses for PWM

MOSFET as a function of VGS and switching optimized power MOSFET (Si6801DQ) versus frequency. conventional (Si6542DQ) and low-threshold

(Si6552DQ) power MOSFETs.

Document Number: 70649 www.vishay.com
Fax Back 408-970-5600 January 1997