Texas Instruments TL16C554A, TL16C554AI ASYNCHRONOUS-COMMUNICATIONS ELEMENT Data Handbook (1) Specification Sheet User Manual

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ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509A – AUGUST 2001 – REVISED JULY 2003

Integrated Asynchronous-Communications Fully Programmable Serial Interface Element Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters

Consists of Four Improved TL16C550C

– Even-, Odd-, or No-Parity Bit

ACEs Plus Steering Logic

– 1-, 1 1/2-, or 2-Stop Bit Generation

In FIFO Mode, Each ACE Transmitter and

– Baud Generation (DC to 1-Mbit Per

Receiver Is Buffered With 16-Byte FIFO to

Second)

Reduce the Number of Interrupts to CPU

False Start Bit Detection

In TL16C450 Mode, Hold and Shift

Complete Status Reporting Capabilities

Registers Eliminate Need for Precise Synchronization Between the CPU and Line Break Generation and Detection Serial Data

Internal Diagnostic Capabilities: Up to 16-MHz Clock Rate for up to 1-Mbaud – Loopback Controls for Communications Operation Link Fault Isolation – Break, Parity, Overrun, Framing Error

Programmable Baud-Rate Generators

Simulation

Which Allow Division of Any Input Reference Clock by 1 to (216–1) and Fully Prioritized Interrupt System Controls Generate an Internal 16 × Clock

Modem Control Functions (CTS, RTS, DSR, Adds or Deletes Standard Asynchronous DTR, RI, and DCD)

Communication Bits (Start, Stop, and

3-State Outputs Provide TTL Drive

Parity) to or From the Serial-Data Stream

Capabilities for Bidirectional Data Bus and Independently Controlled Transmit, Control Bus

Receive, Line Status, and Data Set

Programmable Auto-RTS and Auto-CTS

Interrupts

CTS Controls Transmitter in Auto-CTS

5-V and 3.3-V Operation

Mode, RCV FIFO Contents and Threshold Control RTS in Auto-RTS Mode,

description The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered. The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 216–1. The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2001 – 2003, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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