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Texas Instruments THS10082 Data Sheet

Summary

The THS10082 is a low-power, 10-bit, high-speed (8 MSPS) Analog-to-Digital Converter (ADC) featuring simultaneous sampling of two configurable inputs and an integrated 16-word FIFO. This manual provides comprehensive details on its versatile operation modes for continuous acquisition, single conversion, and auto-scan functions. It is ideally suited for demanding applications requiring high bandwidth and precision, including radar systems, medical imaging, high-speed data acquisition, communications, DSP front-ends, and automotive control.

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查询THS10082供应商

www.ti.com

SLAS254B – MAY 2002 – REVISED NOVEMBER 2002

FEATURES of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are

Simultaneous Sampling of Two Single-Ended

provided.

Signals or One Differential Signal

An external reference can also be chosen to suit the dc

Integrated 16-Word FIFO

accuracy and temperature drift requirements of the

Signal-to-Noise and Distortion Ratio: 59 d B at

application. Two different conversion modes can be

f I = 2 MHz

selected. In the single conversion mode, a single and Differential Nonlinearity Error: ±1 LSB simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion

Integral Nonlinearity Error: ±1 LSB

clock in the single conversion mode is generated internally

Auto-Scan Mode for Two Inputs

using a clock oscillator circuit. In the continuous

3-V or 5-V Digital Interface Compatible conversion mode, an external clock signal is applied to the

CONV_CLK input of the THS10082. The internal clock

Low Power: 216 m W Max

oscillator is switched off in the continuous conversion

5-V Analog Single Supply Operation

mode.

Internal Voltage References 50 PPM/°C

The THS10082C is characterized for operation from 0°C

and ±5% Accuracy

to 70°C, and the THS10082I is characterized for operation

Parallel µC/DSP Interface

from –40°C to 85°C.

APPLICATIONS

DA PACKAGE Radar Applications (TOP VIEW)

Communications

D0 OV_FL

Control Applications

D1 RESET

High-Speed DSP Front-End

D2 AINP

Automotive Applications D3 AINM

D4 REFIN

DESCRIPTION D5 REFOUT

BVDD REFP

The THS10082 is a CMOS, low-power, 10-bit, 8 MSPS

BGND REFM

analog-to-digital converter (ADC). The speed, resolution,

D6 AGND

bandwidth, and single-supply operation are suited for

D7 AVDD

applications in radar, imaging, high-speed acquisition, and

D8 CS0

communications. A multistage pipelined architecture with

D9 CS1

output error correction logic provides for no missing codes

over the full operating temperature range. Internal control RA0 WR (R/W) registers allow for programming the ADC into the desired RA1 RD

mode. The THS10082 consists of two analog inputs, CONV_CLK (CONVST) DVDD which are sampled simultaneously. These inputs can be DATA_AV DGND selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

!" # $%&" !#  '%()$!" *!"&+ *%$"# Copyright  2002, Texas Instruments Incorporated

Page Summary Contents For Texas Instruments THS10082 Data Sheet

Page 1 查询THS10082供应商 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 FEATURES of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are Simultaneous Sampling...
Page 2 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ORDERING INFORMATION These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in PACKAGED DE...
Page 3 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, DVDD = 3.3 V, AVDD = 5 V, VREF = internal (unless otherwise noted) DIGITAL SPEC...
Page 4 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, VREF = internal, fs = 8 MHz, f I = 2 MHz at –1 d B (unless otherwise noted) AC ...
Page 5 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AINP Analog input, single-ended or positive input of differential channel A AINM Analog inpu...
Page 6 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REFOUT 1.5 V REF DATA_AV REFP REFM OV_FL REFIN BVDD Single-Ended 10-Bit and/or FIFO Pipeline D0 Differential 1...
Page 7 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ri re yn am ic an ta l H ar ic is to rt io TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs SAMPLING FREQUE...
Page 8 ri re yn am ic an www.ti.com ta l H ar ic is to rt io SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs SAMPLING FREQUE...
Page 9 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ta l H ar ic is to rt io TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE AND DISTORTION vs vs INPUT FREQUENCY (DIFFERENTIAL) IN...
Page 10 IN ig al -t -N is an is to rt io www.ti.com ig al -t -N is SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE TOTAL HARMONIC DISTORTION INPUT FREQUENCY (DIFFERENTIAL) ...
Page 11 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ig al -t -N is ff ec tiv er f B its TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE EFFECTIVE NUMBER OF BITS vs vs INPUT FREQUENCY (DIFFERENTIAL) SAMPLIN...
Page 12 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS INPUT FREQUENCY (DIFFERENTIAL) 11.0 10.5 ff ec tiv er f B its AVDD = 5 V, DVDD = BVDD = 3 V, fs ...
Page 13 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY IN In te ra l N lin ea ri ty iff er en tia l N lin ea ri ty vs ADC CODE AVDD = 5 V, DVDD = BVDD...
Page 14 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS ag itu ag itu FAST FOURIER TRANSFORM vs FREQUENCY (4096 POINTS) (SINGLE-ENDED MODE) AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8...
Page 15 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 DETAILED DESCRIPTION Reference Voltage The THS10082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to ...
Page 16 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 SINGLE CONVERSION MODE In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion m...
Page 17 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 Sample N Sample N+1 Sample N+2 Sample N+3 Sample N+4 Sample N+5 Sample N+6 Sample N+7 Sample N+8 Channel 1 Channel 1 Channel 1 Channel 1 Channel ...
Page 18 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 DIGITAL OUTPUT DATA FORMAT The digital output data format of the THS10082 can either be in binary format or in twos complement format. The follow...
Page 19 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 FIFO DESCRIPTION In order to facilitate an efficient connection to today’s processors, the THS10082 is supplied with a FIFO. This integrated FIFO...
Page 20 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 READING DATA FROM THE FIFO The THS10082 informs the connected processor via the digital output DATA_AV (data available) that a block of conversio...
Page 21 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ADC CONTROL REGISTER The THS10082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The...
Page 22 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 INITIALIZATION OF THE THS10082 The initialization of the THS10082 should be done according to the configuration flow shown in Figure 34. Start Us...
Page 23 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ADC CONTROL REGISTERS Control Register 0, Write Only (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEST...
Page 24 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 ANALOG INPUT CHANNEL SELECTION The analog input channels of the THS10082 can be selected via bits 3 to 7 of control register 0. One single channe...
Page 25 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 Control Register 1, Write Only (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESERVED OFFSET BIN/2s R/W...
Page 26 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 FIFO TRIGGER LEVEL Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trig...
Page 27 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 DATA_AV Type Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determine...
Page 28 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 Read Timing Parameter (CS0-Controlled)(1) PARAMETER MIN TYP MAX UNIT tsu(R/W) Setup time, R/W high to last CS valid ns ta Access time, last CS va...
Page 29 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 INTERFACING THE THS10082 TO THE TMS320C30/31/33 DSP The following application circuit shows an interface of the THS10082 to the TMS320C30/31/33 ...
Page 30 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 Read Timing Parameter (RD-Controlled) PARAMETER MIN TYP MAX UNIT tsu(CS) Setup time, RD low to last CS valid ns ta Access time, last CS valid to ...
Page 31 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 INTERFACING THE THS10082 TO THE TMS320C6201 DSP The following application circuit shows an interface of the THS10082 to the TMS320C6201. The read...
Page 32 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 VREFP 10-Bit ADC VREFM Figure 41. Differential Input Stage In comparison to the single-ended configuration it can be seen that the voltage (VADC)...
Page 33 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 DC COUPLING An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS10082. The...
Page 34 www.ti.com SLAS254B – MAY 2002 – REVISED NOVEMBER 2002 MECHANICAL DATA DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 38 PINS SHOWN 6,20 8,40 NOM 7,80 0,15 NOM Gage Plane Seating Plane 1,20 MAX 0,10 PI...
Page 35 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing Qty THS10082CDA ACTIVE TS...
Page 36 MECHANICAL DATA MTSS002C – JANUARY 1995 – REVISED DECEMBER 1998 DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE 38 PINS SHOWN 6,20 8,40 NOM 7,80 0,15 NOM Gage Plane Seating Plane 1,20 MAX 0,10 PINS ** DIM A MAX...
Page 37 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and servic...

Manual Details

Brand Texas Instruments
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Published June 17, 2026
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Frequently Asked Questions

What are the operating temperature ranges for the THS10082?

The -THS10082C operates from 0°C to 70°C, while the -THS10082I is characterized for operation from –40°C to 85°C.

How does the ADC handle data overflow?

It features a multistage pipelined architecture with output error correction logic that provides for no missing codes over the full operating temperature range.

What type of inputs can be used and how are they configured?

The THS10082 has two analog inputs (CONVST) that are sampled simultaneously and can be selected individually and configured to single-ended or differential inputs.

What specialized features does the ADC include for system efficiency?

It includes an integrated 16 word deep FIFO, internal temperature drift characteristics, and low power operation (216 mW Max oscillator is switched off in continuous conversion).