Texas Instruments SN74F112 Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset

SN74F112

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 Package Options Include Plastic D OR N PACKAGE (TOP VIEW)

Small-Outline Packages and Standard Plastic 300-mil DIPs

1CLK VCC description 1K 1CLR 1J 2CLR

The SN74F112 contains two independent J-K

1PRE 2CLK

negative-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs regardless of the levels of the

2Q 2PRE

other inputs. When PRE and CLR are inactive

GND 2Q

(high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The SN74F112 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE INPUTS OUTPUTS

PRE CLR CLK

Toggle Q0 Q0

The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date. Copyright  1993, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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