Philips 74F112 Dual J-K Negative Edge-Triggered Flip-Flop Data Manual
Summary
74F112 dual J-K negative edge-triggered flip-flop. Individual J, K, Clock, Set, Reset inputs with true/complementary outputs. 100MHz propagation delay, 15mA supply current at 5V. Active-low async set/reset override clock. Available in 16-pin DIP and SO packages for commercial and industrial ranges. For digital designers implementing sequential logic and frequency dividers.
Page 1 Text Content
INTEGRATED CIRCUITS查询I74F112D供应商
74F112 Dual J-K negative edge-triggered flip-flop
Product specification 1990 Feb 09
IC15 Data Handbook
Page Summary Contents For Philips 74F112 Dual J-K Negative Edge-Triggered Flip-Flop Data Manual
Manual Details
| Brand | Philips |
|---|---|
| Pages | 10 |
| File Size | 86.72 KB |
| Published | July 04, 2026 |
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Frequently Asked Questions
What is the industrial temperature range for the 74F112?
The industrial temperature range is -40°C to +85°C.
How are the outputs set or reset?
Setting the SD input Low sets the output High, and setting the RD input Low resets the output Low, regardless of other inputs.
What initiates an output change?
Output changes are initiated by a high-to-low transition (falling edge) on the CP (clock) input.
What are the recommended operating conditions for V_CC?
The supply voltage V_CC should be between 4.5V (min), 5.0V (nom), and 5.5V (max).